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SRIO gen2 reference design

SRIO gen2 reference design


Last Update

March 26, 2014

Reference Documents

RapidIO II MegaCore Function User Guide (PDF)

Downloadable Reference Design File

Rio2_2x_6250_sys_sv_es_12_1sp1.qar

Introduction

The purpose of this design is to demonstrate how to use Altera Serial RapidIO IP Core pass-through port to generate and receive different type of packet. The reference design is running at x2 modes 6.25 Gbaud data rate. It can be change to any different modes and data rate easily re-generate the Serial RapidIO IP Core. 

The design targets the Stratix V GT Signal Integrity Evaluation Board (Stratix V GT device 5SGTMC7K2F40C2) and is developed with the Altera Quartus II release 13.1 development tool.

This reference design able to generate the following RapidIO transactions types: 

1) NREAD 

2) NWRITEs (non-shareable memory write operations) 

3) SWRITEs (streaming write, double-word only version of NWRITE with less header overhead) 

4) Maintenance Read 

5) Maintenance Write 

6) Maintenance Port Write 

7) Doorbell Messages 

8) Message packet 

9) Response packet w/o data 

10) Response packet with data 

Note: 

1. The reference design dose not able to response to the request packet such as Doorbell, Message, Nread or Maintenance Read and write packets. 

2. The reference design is provided as is and is not supported by Altera. 

High Level Architecture

Figure 1-1 shows a top-level block diagram of the RapidIO reference design implemented on the Altera FPGAs. 

 5/5d/Passthrough_top.png

Figure 1-1 FPGA Reference Design

The Control Unit is system console. The Control Unit runs at a lower frequency than the rest of the design. For the 6.25 Gbaud x2 solution, the RapidIO core runs at 156.25 MHz. The Control Unit had difficulty using this clock speed and this is the reason it was designed as a separate block. In this design the Control Unit is running at 50MHz. 

The Control Unit is system console. The Control Unit runs at a lower frequency than the rest of the design. For the 6.25 Gbaud x2 solution, the RapidIO core runs at 156.25 MHz. The Control Unit had difficulty using this clock speed and this is the reason it was designed as a separate block. In this design the Control Unit is running at 50MHz. 

Control Unit

The following are components used in the Control Unit and a description of their function. 

System Console

Altera's System Console is a TCL console that provides access to hardware modules instantiated in FPGA. It can create powerful verification instruments for the system. It can start, stop or step different procedure to read or write Avalon Memory-Mapped (Avalon-MM) slaves. It can also run JTAG loopback tests. System Console is intended as a low level tool for tasks such as board bring up and device driver debugging. 

JTAG Avalon

This component provides the mechanism for communicating to the System Console. The System Console is the user interface to the RapidIO IP and test application registers. 

Avalon_mm_read_combine

Various bridges that allow communication of the single master port of JTAG Avalon MM port with multiple components with like sRIO IP Core, packet generator and checker etc, by the using of Address Mapping. These are described in more detail in the section, “Testing the Reference Design” and memory mapping. 

RX_BUFFER

This module terminates write bursts and services read bursts which are a result of NWRITEs or NREADs being received by the RapidIO core. The module has a local 32x8Kbyte memory. 

RapidIO MegaCore

The RapidIO MegaCore is the main component in this reference design. It is responsible for establishing a RapidIO link with the link partner. It will also convert the transactions presented to it on the Avalon-MM interfaces into the corresponding RapidIO transactions and transmit them on the RapidIO serial link. On reception, it will convert the RapidIO transactions into Avalon-MM bursts and present these bursts to the corresponding Avalon-MM Slave or Master interfaces.

Pass-through test Logic

Pass-thru port is a custom interface provided by SRIO core to handle packet types/transaction types other than those that it supports. If the SRIO core does not support the type of the packet that it has been asked to receive, then that packet is routed to the Pass-through port rather than the IO Master port. For transmit, the Custom Logical layer is directly connected (rather than routed) to the Pass-through port. The Pass-through test logic is used to test the performance on Pass-through port of RapidIO core. The main components of pass-through test logic are Custom Logical layer (created using the IO Master verilog files) and Pass-through RX_BUFFER. Custom logical layer will directly connect to the Transport layer of RapidIO core through Pass-through port. For more information, please refer SRIO_FPGA_Functional_Document.doc. 

Testing the Reference Design

All of the files, necessary for testing this reference design are included in the zip file “Pass_through_srio_6250_2x_systemconsole_13_1.zip”. 

Un-unzip the Quartus II 13.1 Project

Download and un-zip the Pass_through_srio_6250_2x_systemconsole_13_1.zip file. After unzipping, you will have the following folder structure. Please refer Figure 2-1 : Extracted Packet File image. 

 d/d7/Passthrough_unzip.png

Figure 2 1 Extracted Packet File image


Package Content Description

After extraction, there is a folder named “Pass_through_srio_6250_2x_systemconsole_13_1”. 


Folders Description: 

JTAG_AVALON: JTAG Avalon module 

Phy_mgmt_pll_125: 125MHz pll module 

Sys_pll_156: 156MHz pll module 

Rio2_2x_6250: sRIO IP Core 

Srio_reconfig_ctrl: Reconfiguration Control module 

System_console: System_console tcl file 


Files Description:

Rio2_hw.v: Top level file

Passthrough_test_logic.sv: Traffic generator and packet checker

Avalon_mm_read_combine.v: Avalon MM read/write hop


GUI Interface and Memory Mapping

This section will introduce the GUI interface. 

Note: System Console have to open after program FPGA. 

Open System Console

Step 1: Open System Console under Tool -> System Console -> System Console 

 6/62/Passthrough_systemconsole.png

Figure 3-1 Open System Console

Step 2: Type “cd system_console” and “source main_run.tcl” command to execute the Tcl file and run the GUI interface. See example below. 

 d/dc/Passthrough_system_console.png

Figure 3-1.1 Open System Console


GUI Control Panel

There are two control panels in the GUI. Status_Register control panel and Packet Generator control panel. 

Status_Register control panel includes port status & control register and soft-error recovery relative registers. See figure 3-2.1. 

Note: 

1. Make sure Port_OK LED light is “green” which means port is link up. 

2. OutPort_Enable and InPort_Enable need to be set to 1 in the “Port Control Register” before generate packets.

Packet Generator control panel includes packet parameter setting register, TX packet counters and RX packet counters. See figure 3-2.2.

 0/0e/Passthrough_GUI_status.png

Figure 3 2.1 Status Register Control Panel 

a/aa/Passthrough_GUI_packet_gen.png

 

Figure 3 2.2 Packet Generator Control Panel 

Tcl Console Command

There are two basic read/write commands available for the Tcl Console to read/write particular register.

Reg_read 0xaddress //Register Read

Reg_write 0xaddress 0xdata //Register Write

Memory Map

 e/e8/Passthrough_memory_map1.png

/7/73/Passthrough_memory_map2.png

 

Figure 3-4 Memory Map

Test Steps

Some steps need to be done before generate packets: 

1. Use the “Status_Register” Panel. (See Figure 3 2.1)

2. Check “Port Status Register” port_OK bit is asserted.

3. Check “Port Control Register” port width linkup with 2X mode.

4. Enable input and output port enable bits in “Port Control Register”. That allow data packet go through.

5. Use the “PakcetGenerator” Panel. (See Figure 3 2.2)

6. This panel allows you to generate and receive packet.

7. Configure the packet as below.

NWrite Packet

Following header setting need to be done before start the NWRITE transaction test:

1. Set “Pkt Type” to NWrite.

2. Set “Payload Size”.

3. Set “DestID” number.

4. Set “Transction ID”, optional.

5. Set “Tx Address”, optional.

6. Set “Payload Data”, optional, 32bit.

Data structure is fixed for NWrite packet

Pd_data = {Pakcet counter (4byte), 0’s (2byte), Payload_Data[31:16], Payload_Data…}

Transcetion ID will increment automatically from 0x80 to 0xFF. 

SWrite Packet

Following header setting need to be done before start the SWRITE transaction test:

1. Set “Pkt Type” to SWrite.

2. Set “Payload Size”.

3. Set “DestID” number.

4. Set “Tx Address”, optional. 

5. Set “Payload Data”, optional, 32bit.

Data structure is fixed for SWrite packet

Pd_data = {Pakcet counter (4byte), Payload_Data, Payload_Data, …}

DoorBell Packet

Following header setting need to be done before start the Doorbell transaction test:

1. Set “Pkt Type” to DoorBell.

2. Set “DestID” number. 

3. Set “Transction ID”, optional.

4. Set Information at Tx Address[15:0] field.

Maintenance Read

Following header setting need to be done before start the Maint Read transaction test:

1. Set “Pkt Type” to Maint Read.

2. Set “DestID” number.

3. Set “Transction ID”.

4. Set “Hop count” number.

5. Set “Tx Address” [23:0] 24bit.

Maintenance Write

Following header setting need to be done before start the Maint Write transaction test:

1. Set “Pkt Type” to Maint Write.

2. Set “DestID” number.

3. Set “Transction ID”.

4. Set “Hop count” number.

5. Set “Tx Address”.

6. Set “Payload Data” 32bit.

Port Write

Following header setting need to be done before start the PortWrite transaction test:

1. Set “Pkt Type” to Maint Write.

2. Set “DestID” number.

3. Set “Transction ID”.

4. Set “Hop count” number.

5. Set “Tx Address”.

6. Set “Payload Data” 32bit.

Receive Maintenance Read Response Packet

“Packet Generator Setting” Panel -> “Read” button will read the last maintenance read response packet data which shows on “Maint Read Data” 64bit long.

 

Message Packet

Following header setting need to be done before start the Message transaction test:

1. Set “Pkt Type” to Maint Write.

2. Set “DestID” number.

3. Set 4bit Len, 4bit Size, 2bit letter, 2bit Mbox, 4bit message in “Tx Address” field. Total of 16bit.

4. Set “Payload Data” 32bit.

Response Packet w/o Data

Following header setting need to be done before start the SWRITE transaction test:

7. Set “Pkt Type” to Maint Write.

8. Set “DestID” number.

9. Set 4bit Status, and 8bit targetID in “Tx Address” field. Total of 12bit.


Response Packet with Data

Following header setting need to be done before start the SWRITE transaction test:

10. Set “Pkt Type” to Maint Write.

11. Set “DestID” number.

12. Set 4bit Status, and 8bit targetID in “Tx Address” field. Total of 12bit.

13. Set “Payload Data” 32bit.

Note: All packet generator setting needs to press “Write” button to write to the register.

Disclaimer

© [2014] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate. 

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