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Insert non-formatted text here= Transceiver Design Examples = This page is a collection of tranciever design examples for Altera products.

Stratix V GT

The Stratix V GT is optimized for applications with 28.05Gbps transceivers requiring ultra-high bandwidth and performance, such as 40G/100G/400G applications. Here is some more text to fill this up so it looks a little better. Lorem ipsum something I can't remember. The Stratix V is a nice FPGA. Word.

4 Ch. Multi-PRBS at 25Gbps

This is some text which would give the user a small overview of the design. Perhaps we don't need as much detail in the title. In fact, if you think about it the more detail we put in the title the more cluttered things get. However we don't want to remove too much info from the title because then the designs will be hard to find.

4 Ch. Multi-PRBS at 25Gbps

This is some text which would give the user a small overview of the design. Perhaps we don't need as much detail in the title. In fact, if you think about it the more detail we put in the title the more cluttered things get. However we don't want to remove too much info from the title because then the designs will be hard to find.

fds

StratixV I/O dynamic delay chain design example which is the extension to the Stratix IV version. This design example aims to show how to configure for StratixV dynamic delay chain which is different from StratixIV like the configuration cycles, position of LSB and MSB bits, position for output/input/reserved bits. Attached is the QuartusII design and "how-to" document.


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Last update:
‎06-21-2019 09:22 PM
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