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Scalable LL Ethernet 10G MAC with 10G BaseR PHY Design Example

Scalable LL Ethernet 10G MAC with 10G BaseR PHY Design Example

Last Major Update 

October 20, 2014



This note describes a demo design that demonstrates the functionality of the Altera Scalable LL Ethernet 10G MAC with 10G BaseR PHY. This demo example is able to support up to 12 channels of Ethernet ports. Stratix V SI hardware kits is use for the demo. 

Software and Hardware Requirements

Altera uses the following hardware and software to test the scalable LL Ethernet 10G MAC with 10G BaseR PHY design example and testbench:

■ Altera Complete Design Suite 14.0 

■ Stratix V GX Transceiver SI Development Board (EP5SGXEA7N2F40C2N) 

■ ModelSim-SE 

■ USB-Blaster cable 

■ Windows- or Linux-based system console

Procedures to run the design with Modelsim software

The Scalable LL Ethernet 10G MAC with 10G BaseR PHY design example comes with a testbench for simulation verification. Below are the steps to run the simulation.

1. Download and unzip the demo project:

2. Launch Modelsim-SE 10.2b and change the directory to Scalable_LL_Mac_10G_BaseR\testbench\Modelsim\testcase.

3. In the TCL console window, type the below command:

do tb_run.tcl

4. At the end of the simulation, Modelsim simulator will provide a list of transmitted packets and received packets. If the number of transmitted packets is equivalent to the received packets, the simulation will show “Simulation PASSED”.

Procedures to run the hardware design

The design example package comes with pre-generated RTL files which able to support up to 12 channels. To use the design example, perform the following steps:

1. Download and unzip the demo project: (refer to the project link above).

2. Change directory to Scalable_LL_Mac_10G_BaseR.

3. Launch the Quartus II 14.0 software and open the project file altera_eth_top.qpf.

4. Click Start Compilation on the Processing menu to compile the design example. A .sof file will be generated once the compilation is complete.

5. Program the .sof file onto the FPGA.

6. The design example is designed to use the board DIP and switches to control the system resets.Please refer to the design .qsf file to check for the resets pin assignemnt.

7. LEDs on the board will on to indicate the link is ready.

NOTE: The pin assignment, device setting and register map for 10 channels have been set in .qsf file due to the limitation of the number of ports available on the Stratix V SI development kit. 

8. Launch system console from Qsys. 

9. Browse to the SystemConsole directory in the System Console command shell. 

10. Type the command “source main.tcl “ followed by ENTER key to launch the reference design command list.

14. user can refer to the test functions available in main.tcl file to perform the following tests:

i) TEST_PHYSERIAL_LOOPBACK {channel speed_test burst_size} - PHY internal serial loopback test with internal traffic generator

ii) TEST_SMA_LB {channel speed_test burst_size} - SMA loopback test with internal traffic generator

iii) TEST_SFPP_WO_ENA_ST_LOOPBACK {channel burst_size} - SFP port loopback test with internal traffic generator.

iv) TEST_SFPP_ENA_ST_LOOPBACK {channel} - Avalon-ST reverse loopback test with external tester via SFP port.

15. For more detail information related to this design example, please refer to the Scalable_LLMAC_10gBaseR_design_example_user_guide.pdf


© [2011] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.

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Last update:
‎06-26-2019 09:06 PM
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