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Scalable Multispeed 10M-10Gbps Ethernet with 1588 using 1G/10G PHY Design Ex

Scalable Multispeed 10M-10Gbps Ethernet with 1588 using 1G/10G PHY Design Example



Last Major Update 

December 11, 2013

 


Introduction

This note describes a demo design that demonstrates the functionality of the Altera Multispeed 10M/100M/1G/10Gbps Ethernet (MAC +1G/10G PHY) IP with IEEE 1588 features and able to support for 4 speeds in both manual and automatic mode. This demo example is able to support up to 12 channels of Ethernet ports. Stratix V SI hardware kits is use for the demo. 

Software and Hardware Requirements

Altera uses the following hardware and software to test the scalable 1G/10GbE MAC with IEEE 1588v2 design example and testbench:


■ Altera Complete Design Suite 13.1 IB162 

■ Stratix V GX Transceiver SI Development Board (EP5SGXEA7N2F40C2N) 

■ ModelSim-SE 10.2b 

■ VCS 2013.06-1 

■ USB-Blaster cable 

■ Windows- or Linux-based system console 

■ Clock control ( refer to http://www.altera.com/products/devkits/altera/kit-transceiver-si-stratix-v.html to install the Kit installation for v11.1.2 )


Procedures to run the hardware design

The design example package comes with pre-generated RTL files which able to support up to 12 channels. To use the design example, perform the following steps:

1. Download and unzip the demo project: altera_eth_1g10g_lineside_w_1588.

2. Change directory to altera_eth_1G10g_lineside_w_1588.

3. Launch the Quartus II 13.1 software and open the project file altera_eth_top_.qpf.

4. Click Start Compilation on the Processing menu to compile the design example. A .sof file will be generated once the compilation is complete.

5. Program the .sof file onto the FPGA.

6. Open the clock control and change the target frequency setting as below (refer to Figure 1 and Figure 2):

Y3 - 322.2656 MHz

Y4 – 125MHz


8/83/Figure4and5_clockcontrol_1G10G.png


7. The design example is designed to use In-System Source and Probe from Quartus to control the system reset. Launch the In-System Source and Probe from Tools.

8. Make sure the proper device is selected. There will be 10 source switch for triggering. S0 is for master_reset_n, S1 is for channel_reset_1, S2 is for channel_reset_2, so on and so forth.

9. Set S0 to 1 and set 1 to all source switches depending on the number of channels instantiated. Example, if 2 channels are instantiated, set 1 to S1 and S2.

10. LED0 on the board will on once S0 is set to 1. LED1 will be on once S1 is set to 1. The rest of the LEDs will be on depending on the number of channels instantiated and reset.

NOTE: The pin assignment, device setting and register map for 10 channels have been set in .qsf file due to the limitation of the number of ports available on the Stratix V SI development kit. 

11. Launch system console from Qsys. 

12. Browse to the SystemConsole_w1588 directory in the System Console command shell. 

13. Type the command “source main.tcl “ followed by ENTER key to launch the reference design command list.

14. user can refer to the test functions available in main.tcl file to perform the following tests:

i) TEST_PHYSERIAL_LOOPBACK {channel speed_test burst_size} - PHY internal serial loopback

ii) TEST_SMA_LB {channel speed_test burst_size} - SMA loopback

iii)TEST_1588 {from_channel to_channel speed_test} - SMA loopback between 2 channels (1. master ,2 Slave).


15. For more detail information related to this design example, please refer to the  Scalable_1G10GbE_1588_Design_Example_User_Guide


Disclaimer

© [2011] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.

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Last update:
‎06-26-2019 09:11 PM
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