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Scalable Multispeed 10M-10Gbps Ethernet without 1588 using 1G/10G PHY Design Ex

Scalable Multispeed 10M-10Gbps Ethernet without 1588 using 1G/10G PHY Design Example


Last Major Update 

December 11, 2013

 

Introduction

This note describes a demo design that demonstrates the functionality of the Altera Multispeed 10M/100M/1G/10Gbps Ethernet (MAC +1G/10G PHY) IP which able to support for 4 speeds in both manual and automatic mode. Stratix V SI hardware kits will be used for the demo. 

Software and Hardware Requirements

Altera uses the following hardware and software to test the scalable Quadspeed Ethernet design example and testbench:


■ Altera Complete Design Suite 13.1 IB162 

■ Stratix V GX Transceiver SI Development Board (EP5SGXEA7N2F40C2N) 

■ ModelSim-SE 10.2b 

■ VCS 2013.06-1 

■ USB-Blaster cable 

■ Windows- or Linux-based system console 

■ Clock control ( refer to http://www.altera.com/products/devkits/altera/kit-transceiver-si-stratix-v.html to install the Kit installation for v11.1.2 )


Procedures to run the hardware design

The design example package comes with pre-generated RTL files which can support up to 12 channels. To use the design example, perform the following steps:

1. Download and unzip the demo project: Altera_eth_1g10g_lineside.zip

2. Download the altera_eth_top.sof file provided into Stratix V SI board. 

3. After download the .sof file, open the clock control and change the target frequency setting as below (refer to Figure 1 and Figure 2):

Y3 - 322.2656 MHz

Y4 – 125MHz

8/83/Figure4and5_clockcontrol_1G10G.png


4. Press PB0 push button to reset the system. System must be hard reset before proceed. NOTE: The pin assignment, device setting and register map for 12 channels have been set in .qsf file). 

5. Launch system console from Qsys. 

6. Browse to the SystemConsole_wo1588 directory in the System Console command shell.

7. Type the command “source main.tcl “ followed by ENTER key to launch the reference design command list.

8. User can refer to the test functions available in main.tcl file to perform the following tests:

i) TEST_PHYSERIAL_LOOPBACK {channel speed_test burst_size} - PHY internal serial loopback

ii) TEST_SMA_LB {channel speed_test burst_size} - SMA loopback

iii)TEST_1588 {from_channel to_channel speed_test} - SMA loopback between 2 channels (1. master ,2 Slave).


9. For more detail information related to this design example, please refer to the Scalable_1G10GbE_Design_Example_User_Guide


Disclaimer

© [2011] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.

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Last update:
‎06-26-2019 09:12 PM
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