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Scalable TSE with 1588 Design Example

Scalable TSE with 1588 Design Example



Last Major Update 

March 27, 2014

 

Introduction

This note describes a demo design that demonstrates the functionality of the Altera Triple Speed Ethernet IP with IEEE 1588 features. This demo example is able to support up to 10 channels of Ethernet ports. Stratix V SI hardware kits is use for the demo. 

Software and Hardware Requirements

Altera uses the following hardware and software to test the scalable TSE with IEEE 1588v2 design example and testbench:


■ Altera Complete Design Suite 13.1 IB162 

■ Stratix V GX Transceiver SI Development Board (EP5SGXEA7N2F40C2N) 

■ ModelSim-SE 10.2b 

■ USB-Blaster cable 

■ Windows- or Linux-based system console 

■ Clock control ( refer to http://www.altera.com/products/devkits/altera/kit-transceiver-si-stratix-v.html to install the Kit installation for v11.1.2 )


Procedures to run the hardware design

The design example package comes with pre-generated RTL files which able to support up to 10 channels. To use the design example, perform the following steps:

1. Download and unzip the demo project: altera_eth_tse_w_1588.

2. Change directory to altera_eth_tse_w_1588.

3. Launch the Quartus II 13.1 software and open the project file altera_eth_top.qpf.

4. Click Start Compilation on the Processing menu to compile the design example. A .sof file will be generated once the compilation is complete.

5. Program the .sof file onto the FPGA.

6. Open the clock control and change the target frequency setting as below (refer to Figure 1):

Y4 – 125MHz

b/bf/Clock_control.png


7. The design example is designed to use In-System Source and Probe from Quartus to control the system reset. Launch the In-System Source and Probe from Tools.

8. LEDs on the board will on to indicate the link is ready.

NOTE: The pin assignment, device setting and register map for 10 channels have been set in .qsf file due to the limitation of the number of ports available on the Stratix V SI development kit. 

11. Launch system console from Qsys. 

12. Browse to the SystemConsole directory in the System Console command shell. 

13. Type the command “source main.tcl “ followed by ENTER key to launch the reference design command list.

14. user can refer to the test functions available in main.tcl file to perform the following tests:

i) TEST_PHYSERIAL_LOOPBACK {channel speed_test burst_size} - PHY internal serial loopback

ii) TEST_SMA_LB {channel speed_test burst_size} - SMA loopback

iii)TEST_1588 {from_channel to_channel speed_test} - SMA loopback between 2 channels (1. master ,2 Slave).



Disclaimer

© [2011] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.

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Last update:
‎06-26-2019 09:14 PM
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