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Scalable TSE without 1588 Design Example

Scalable TSE without 1588 Design Example


Last Major Update 

June 12, 2014

 

Introduction

This note describes a demo design that demonstrates the functionality of the Altera Triple Speed Ethernet IP without IEEE 1588 features. This demo example is able to support up to 10 channels of Ethernet ports. Stratix V SI hardware kits is use for the demo. 

Software and Hardware Requirements

Altera uses the following hardware and software to test the scalable TSE without IEEE 1588v2 design example and testbench:


■ Altera Complete Design Suite 13.1 IB162 

■ Stratix V GX Transceiver SI Development Board (EP5SGXEA7N2F40C2N) 

■ ModelSim-SE 10.2b 

■ USB-Blaster cable 

■ Windows- or Linux-based system console 

■ Clock control ( refer to http://www.altera.com/products/devkits/altera/kit-transceiver-si-stratix-v.html to install the Kit installation for v11.1.2 )


Procedures to run the design with Modelsim software

The scalable TSE without IEEE 1588v2 design example comes with a testbench for simulation verification. Below are the steps to run the simulation.

1. Download and unzip the demo project: altera_eth_tse_wo_1588

2. Change directory to altera_eth_tse_wo_1588.

3. Launch the Quartus II 13.1 software and open the project file altera_eth_top.qpf.

4. There are 2 testbench provided in this design example.

Testcase1: Manual speed change between 1G/100M/10M in SGMII or 1G in 1000Base-X mode with auto negotiation disable


- Circular loopback


- SGMII_1000BASEX parameter in default_test_parameter.sv file: SGMII_1000BASEX ( 1-SGMII, 0-1000BaseX)


- To change number of channels: modify the parameter NUM_CHANNELS in default_test_parameter.sv file


Testcase2:2 channels design with manual speed change between 1G/100M/10M in SGMII mode

or 1G in1000Base-X mode with auto negotiation enable


- For SGMII: channel 0 in SGMII MAC mode, channel 1 in SGMII PHY mode.


- NUM_CHANNELS = 2


- To choose SGMII or 1000 BaseAX mode for 1G, go to default_test_parameter.sv file,

change parameter SGMII_1000BASEX ( 1-SGMII, 0-1000BaseX)


5. Launch Modelsim-SE 10.2b and change the directory to altera_eth_tse_wo_1588/testbench/testcase1 or altera_eth_tse_wo_1588/testbench/testcase2.

6. In the TCL console window, type the below command:

do tb_run.tcl

7. At the end of the simulation, Modelsim simulator will provide a list of transmitted packets and received packets. If the number of transmitted packets is equivalent to the received packets, the simulation will show “Simulation PASSED”.

Procedures to run the hardware design

The design example package comes with pre-generated RTL files which able to support up to 10 channels. To use the design example, perform the following steps:

1. Download and unzip the demo project: (refer to the project link above).

2. Change directory to altera_eth_tse_wo_1588.

3. Launch the Quartus II 13.1 software and open the project file altera_eth_top.qpf.

4. Click Start Compilation on the Processing menu to compile the design example. A .sof file will be generated once the compilation is complete.

5. Program the .sof file onto the FPGA.

6. Open the clock control and change the target frequency setting as below (refer to Figure 1): b/bf/Clock_control.png

Y4 – 125MHz


7. The design example is designed to use In-System Source and Probe from Quartus to control the system reset. Launch the In-System Source and Probe from Tools.

8. LEDs on the board will on to indicate the link is ready.

NOTE: The pin assignment, device setting and register map for 10 channels have been set in .qsf file due to the limitation of the number of ports available on the Stratix V SI development kit. 

11. Launch system console from Qsys. 

12. Browse to the SystemConsole directory in the System Console command shell. 

13. Type the command “source main.tcl “ followed by ENTER key to launch the reference design command list.

14. user can refer to the test functions available in main.tcl file to perform the following tests:

i) TEST_PHYSERIAL_LOOPBACK {channel speed_test burst_size} - PHY internal serial loopback

ii) TEST_SMA_LB {channel speed_test burst_size} - SMA loopback

iii)TEST_1588 {from_channel to_channel speed_test} - SMA loopback between 2 channels (1. master ,2 Slave).



Disclaimer

© [2011] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.

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Last update:
‎06-26-2019 09:15 PM
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