The SerialLite III Streaming MegaCore function includes Altera’s technology leading transceivers PMA, PCS, and MAC layers. The PCS and PMA layers are hardened within the Stratix® V and Arria®V devices saving customers from 20% to 50% of FPGA logic resources. In addition to resource savings, the hardened PCS/PMA functionality enables much easier timing closure for all types of designs. The SerialLite III protocol was designed to provide the necessary reliability, low latency and overhead, and scalability to ensure that data is transferred in the most efficient and robustmanner to maintain low bit error rates required by today’s systems.
This demo design demonstrates the Altera®SerialLite III streaming Source and Sink IP solutions on an Arria V GZ device (5AGZME5K2F40C3). It includes a simplex 16-lane Source core and a simplex 16-lane Sink core. Since we do not have a hardware platform using 5AGZME5K2F40C3 with 16 lanes accessible by user to perform external loopback from Source to Sink, this demo is designed to demonstrate that SerialLite III streaming Source or Sink core can easily pass timing closure with 16x10.3125Gbps configuration which client side user data interface is as wide as 1024-bit.
SerialLite III Streaming MegaCore IP Overview
The SerialLiteIII Streaming MegaCore is a high bandwidth serial protocol that provides two clocking options to provide the flexibility needed for a variety of streaming applications.
> Standard Clocking Scheme (SCS)
> Advanced Clocking Scheme (ACS)
This demo design uses Standard Clocking Scheme which functional block diagram is shown below:
The SerialLiteIII Streaming MegaCore uses hardened Interlaken PHY IP technology.For detailed information about Altera Interlaken PHY IP, please refer to its User Guide available from the link: http://www.altera.com/literature/ug/xcvr_user_guide.pdf The Interlaken PHY IP has PMA and PCS. The interface bus width between PMA and PCSis configured to use 40-bit in SerialLite III MegaCore. The TX parallel clock used by Serializer to receive data from 40-bit parallel bus is derived from Transceiver Reference Clock as shown below. The RX parallel clock used by the DeSerializer is derived from CDR recovered clock coming from the data stream.
This demo design has an independent simplex Source core and an independent simplex Sink core. This Source core used in this demo design is generated from MegaWizard using below configuration. The Sink core used in this demo design shares the same configuration as Source core except the “Direction:” parameter is selected as “Sink”.
Please note that this hardware demo is designed toprovide a flexible system testing platform and reference design. We have done alimited number of testing with an intention to demonstrate the system packetprocessing capability. If you need support to use this Hardware Demo or reportbugs, please open service request ticket through Altera MySupport Account. Altera MySupport Website