Community
cancel
Showing results for 
Search instead for 
Did you mean: 

SerialLiteIII Streaming Core Demo Design using QSFP on PCIe dev kit

SerialLiteIII Streaming Core Demo Design using QSFP on PCIe dev kit


Downloadable Design Examples

Quartus 13.0 SerialLite III Streaming Core Demo Design using QSFP on Stratix V PCIe Devkit

Reference Documents

SerialLite III Streaming MegaCore User Guide

Stratix V FPGA Development Kit (also called PCIe Dev Kit)

Introduction

The Altera Serialite III Streaming MegaCore® function is a lightweight protocol suitable for high bandwidth streaming data in chip-to-chip, board-to-board, and backplane applications. Common streaming applications include radar processing, video, and imaging. These applications have stringent characteristics in that the data must be processed seamlessly and reliably across a serial lane. The SerialLite III Streaming IP utilizes Altera’s transceiver technologies, hardened Interlaken PHY IP, and supports 1~24 lanes providing aggregate bandwidths well over 100 Gbps.

The SerialLite III Streaming MegaCore function incorporates a physical coding sublayer (PCS), a physical media attachment (PMA), and a media access control (MAC) block. The MegaCore function transmits and receives Avalon-ST data on its FPGA fabric interface.

The figure below shows the typical system application diagram.

b/be/SLIII_system_application.JPG



This example design is to demonstrate the SerialLite III Streaming MegaCore functionality using QSFP loopback on a Stratix V GX FPGA Development Kit, also called PCIe Dev Kit. This design provides a flexible test and demonstration platform which effectively control, test, and monitor the streaming data transmitted and received via duplex 2 x 10.3125Gbps transceiver lanes.

Clocking Modes

The SerialLite III Streaming MegaCore supports two clocking mode options: standard and advanced clocking mode. You can select the mode through the parameter editor in the MegaWizard Plug-In Manager. Standard clocking mode is selected in this hardware demonstration design.

Standard Clocking Mode

The Standard Clocking Mode is designed to operate SerialLite III in a pure streaming fashion, exactly replicating the source input data at the sink output. This is achieved through outputting a user clock at both the Source and Sink core for the user interface. In this mode, the core utilizes a clock generator (fPLL) to provide core clock and user clock. The following diagram shows the standard clocking mode in a simplex configuraion. 


6/6e/SLIII_standard_clocking_r2.jpg

7/7a/SLIII_standard_clocking_notes.jpg


Advanced Clocking Mode

The Advanced Clocking Mode, not only allows the User Interface clock to be derived from a clock source other than Source transceiver crystal oscillator, but also eliminates the need of fPLLs used both inside Source and Sink cores. The Advanced Clocking Mode provides another method to transfer data based on slight modifications within the SerialLite III clocking architecture. The following diagram shows the Advanced Clocking Mode.



6/60/SLIII_advanced_clocking.jpg

6/6f/SLIII_advanced_clocking_notes_r2.jpg


Interlaken PHY IP Core

The Interlaken PHY IP Core is a key component that is used within the SerialLite III Streaming IP core. Refer to the Interlaken PHY IP Core chapter in the Transceiver PHY IP Core User Guide available online at: Transceiver PHY IP Core User Guide

The Interlaken PHY IP includes two layers: the PMA layer and the PCS layer. The transmit parallel clock (TX_CLKOUT) and receive parallel clock (RX_CLKOUT) are calculated as follows:

  • Lane Data Rate / PMA Interface Width (40)

The following diagram shows the block diagram of the Interlaken PHY IP core.

5/51/Streaming_core_parameters.jpg


Streaming MagaCore Parameters

The following shows the parameter values selected in the verilog top module of the hardare demonstration design.This demo design uses the Standard Clocking Mode.

5/51/Streaming_core_parameters.jpg



Quick System Setup Guide

The system setup consists of three parts:

• Stratix V GX FPGA Development Kit board 

• QSFP optical transceiver module with loopback 

• USB-Blaster or USB-BlasterII programming cable 

The Stratix V GX FPGA development board requires minimum hardware setup: 

1. A QSFP loopback module is plugged into a QSFP module cage.

2. Connect USB-Blaster/USB-BlasterII cable between host PC and the FPGA board. 

3. Connect FPGA power supply cable with adaptor to provide 19V DC voltage. 


 5/52/SV_FPGA_PCIe_board_r3.jpg


Build software, Download SOF and ELF

The following shows the directories of the hardware demonstration design example. 

a/a2/Demo_directory_tree_r2.jpg



Two easy-to-use script files are provided under software directory: batch_script.sh and rerun.sh.


When you build the design for the first time, you run this script. This script file builds the application software, download the SOF and ELF files, and displays the demonstration menu in a nios2 terminal. If you have multiple USB programming cables, pass in a cable name as shown in the example below:

e.g: ./batch_script.sh USB-Blaster[USB-2] (Note: the cable name 'USB-Blaster[USB-2]' should not include any space)

If you have multiple USB programming cables and are not sure of the cable name, use 'jtagconfig' command in a nios2 terminal to get the correct cable.

If you have only one USB programming cable, then run the script without a cable name.

The following is the nios2 terminal screenshot, showing the application software build.




When the application software is already built, you run this script. This script just downloads the SOF and ELF files and displays the demonstration menu in a nios2 terminal, without building the software. If you have multiple USB programming cables, pass in a cable name as shown in the example below:

e.g: ./rerun.sh USB-Blaster[USB-2] (Note: the cable name 'USB-Blaster[USB-2]' should not include any space)

If you have only one USB programming cable, then run the script without a cable name.

The folllowing is the nios2 terminal screenshot that shows the FPGA and Nios II processor programming.



Viewing the Results

The following demonstration menu is displayed in a nios2 terminal when the SOF and ELF files are downloaded successfully. 

2/2b/Menu_screenshot_r2.jpg


When you select option 1, the data generator immediately starts sending data. The nios2 terminal displays the total words transmitted and recived, and the total transmission and reception errors. Below is the screenshot captured with option 1 selected. 

1/1c/Menu_option1_screenshot.JPG

Version history
Revision #:
1 of 1
Last update:
‎06-26-2019 09:17 PM
Updated by:
 
Contributors