Simulate Arria V Native PHY IP Rate Match FIFO under clock comp condition

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Simulate Arria V Native PHY IP Rate Match FIFO under clock compensation condition

This article descries how to simulate rate matching of the Rate Match FIFO in the Arria V standard PCS by hacking the simulation model.

This trick is useful to understand how the Rate Match FIFO work. But you need to understand the trick breaks the clock topology of the PHY IP, and this trick should not be used for other purposes.

Design Overview

On real devices, the write side of the rate match FIFO is clocked by the RX parallel recovered clock, and the read side of the rate match FIFO is clocked by the TX parallel clock. But in the simulation model, both write and read clocks are synchronous to the TX parallel clock due to the limitation of the CDR modeling. To generate clock compensation condition in the simulation model, the frequency of the FIFO read clock is needed to be higher / lower than the TX parallel clock frequency. You can find the FIFO read clock named 'txpmaclk' in '[instance name]_sim/altera_xcvr_native_av/av_hssi_8g_rx_pcs_rbc.sv', and the txpmaclk is fed to arriav_hssi_8g_rx_pcs module. To change the FIFO read clock frequency, add new clock txpmaclk_ppm, and feed the new clock to arriav_hssi_8g_rx_pcs module instead of txpmaclk. Now, you have the control of the FIFO read clock.

0/03/RMFIFO_ClockGen.PNG

Here is an example of txpmaclk_ppm clock generation circuit. In this example, the period of the new FIFO read clock txpmaclk_ppm is set to 8.002 ns because the original clock period was 8.000 ns, and the clock frequency difference is - 250 ppm. Since the FIFO read clock is slower than the FIFO write clock, the rate match FIFO initiates SKIP code deletion. If you set the period of the txpmaclk_ppm to 7.998 ns, the FIFO initiates SKIP code insertion. Please note that the period of the txpmaclk depends on the PHY IP settings. You need to run simulation to know the txpmaclk period of your Native PHY IP. 

// Rate Match FIFO Testing ------------------------------------------------------------------------

reg txpmaclk_ppm = 1'h0;

// - 250 ppm for deletion testing

always begin

#4.001 txpmaclk_ppm <= ~txpmaclk_ppm; // timescale 1 ns, This period must be almost same as txpmaclk

end

// + 250 ppm for insertion testing

// always begin

// #3.999 txpmaclk_ppm <= ~txpmaclk_ppm; // timescale 1 ns, This period must be almost same as txpmaclk

// end

// ------------------------------------------------------------------------- Rate Match FIFO Testing

If you need higher resolution than the simulation tool can handle (i.e. < 1 ps), you can generate discrete frequencies by creating a gated clock like below. 

// Rate Match FIFO Testing ------------------------------------------------------------------------

reg txpmaclk_ppm = 1'h0;

reg clk = 1'h0;

reg [15:0] clk_cnt = 16'h0;

always begin

#2 clk <= ~clk; // timescale 1ns, This period must be a half of txpmaclk

end

always @(posedge clk or negedge clk) begin

if (clk_cnt == 16'd39999)

clk_cnt <= 16'h0;

else

clk_cnt <= clk_cnt + 1'h1;

end

// +100 ppm for insertion testing

always @(posedge clk or negedge clk) begin

if (clk_cnt == 16'd39999)

txpmaclk_ppm <= ~txpmaclk_ppm;

else if (clk_cnt == 16'd39997)

txpmaclk_ppm <= ~txpmaclk_ppm;

else if (clk_cnt[0] == 1'h0)

txpmaclk_ppm <= ~txpmaclk_ppm;

else

txpmaclk_ppm <= txpmaclk_ppm;

end

/*

// -100 ppm for deletion testing

always @(posedge clk or negedge clk) begin

if (clk_cnt >= 16'd39996)

txpmaclk_ppm <= txpmaclk_ppm;

else if (clk_cnt[0] == 1'h0)

txpmaclk_ppm <= ~txpmaclk_ppm;

else

txpmaclk_ppm <= txpmaclk_ppm;

end

*/

// ------------------------------------------------------------------------- Rate Match FIFO Testing

Design File

ArriaV NativePHY RMFIFO GIGEmode.zip

To run the testbench with ModelSim, follow instructions.

1. Extract the archive file
2. Open ModelSim
3. Change directory to [extracted folder]/ArriaV_NativePHY_RMFIFO_GIGEmode/src/simulation/modelsim
4. Type "do run_tb_deletion.tcl" in the console of the ModleSim to run - 250 ppm clock compensation scenario
5. Type "do run_tb_insertion.tcl" in the console of the ModleSim to run + 250 ppm clock compensation scenario
6. Type "do run_tb_deletion_100ppm.tcl" in the console of the ModleSim to run - 100 ppm clock compensation scenario
7. Type "do run_tb_insertion_100ppm.tcl" in the console of the ModleSim to run + 100 ppm clock compensation scenario

See Also

Altera Transceiver PHY IP Core User Guide (PDF) 

Arria V Device Handbook, Volume 2: Transceivers (PDF)

Key Words

Rate Matching, Rate Match FIFO, Insertion, Deletion, Clock Compensation, Arria V Native PHY IP