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Single-Port 1G/10G Ethernet hardware demo

Single-Port 1G/10G Ethernet hardware demo



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Last Major Update 

January 1, 2013

 

Introduction

This note describes a demo design that demonstrates the functionality of the Altera 1G/10Gbps Ethernet IP which able to switch from 1G to 10Gbps speed and vice versa for both manual and automatic mode. Two Stratix V SI hardware kits will be used for the demo: Board B which generate packets data to Board A through SFP+ module(FTLX8571D3BCV) and loopback at Avalon ST interface of Board A and then the data will be received back by Board B.

[Note: A scalable design example implementing 1G/10G Ethernet that you can integrate into your own, custom design is available on this page.]


Internal traffic generator module has been included in the design to generate either a fixed /random packets data and there is a traffic monitor module to check for the data received and calculate for the throughput to indicate the changes in speed of the 1G/10Gbps IP.


Tool Requirements

The following sections describe tool requirements for the hardware demo. 

■ 2 Stratix V SI hardware kits (5SGXEA7N2CF40C2) 

■ Finisar SFP+ (FTLX8571D3BCV) optical cable. 

■ USB-Blaster cable 

■ Quartus II 12.1 

■ Windows- or Linux-based system console 

■ Clock control ( refer to http://www.altera.com/products/devkits/altera/kit-transceiver-si-stratix-v.html to install the Kit installation for v11.1.2 )


SV Transceiver Signal Integrity Development Kit Hardware setup


Procedures to run the hardware design

Download and unzip the demo project: File:Single port 1G 10G hardware demo.zip for Quartus II 12.1


Board A configuration steps

1.Download the altera_eth_10g_mac_base_kr_top.sof file provided into Stratix V SI Board A.

2. After download the .sof file, open the clock control and change the target frequency setting as below (refer to Figure 4 and Figure 5):

Y3 - 322.2656 MHz

Y4 – 125MHz

3. Press PB0 push button to reset the system. System must be hard reset before proceed. If user connects the SFP+ module with SFP optical loopback cable, user should expect to see LED 7 and LED 8 will LIT as 

• LED 7 – led link is up 

• LED 8 – rx_data_ready is up.

(After hard reset, the Ethernet is in 10G mode).

4. Enable the Avalon-ST loopback module. a. Launch system console: open QSYS Tools System Console [ENTER] b. Browse to the DEMO directory in the System Console command shell. c. Type the command “source demo.tcl “ followed by ENTER key to launch the reference design command list. d.Type the command “EN_AVALON_ST_LOOPBACK” to enable the Avalon ST loopback module



Board B configuration steps

1.Download the altera_eth_10g_mac_base_kr_top.sof file provided into Stratix V SI Board B.

2. After download the .sof file, open the clock control and change the target frequency setting as

Y3 - 322.2656 MHz

Y4 – 125MHz

3. Press PB0 push button to reset the system. System must be hard reset before proceed. If user connects the SFP+ module with SFP optical loopback cable, user should expect to see LED 7 and LED 8 will LIT as • LED 7 – led link is up • LED 8 – rx_data_ready is up.

(After hard reset, the Ethernet is in 10G mode).

4. Connect both board together with a SFP+ optical cable. LED7 and LED8 will LIT on both board.

5. Board B will then be manually forced to change the speed to 1G mode by following steps below: a. Launch system console: open QSYS Tools System Console [ENTER] b. Browse to the DEMO directory in the System Console command shell. c. Type the command “source demo.tcl “ followed by ENTER key to launch the reference design command list. d. Type the command “CONFIGURE_1G” to write to the 1G/10G PHY IP registers, “RESET SEQ” and “SEQ Force Mode[2:0]” to reset the the sequencer , initiate PCS reconfiguration and forces the sequencer to 1G protocol.

e. Once it has been configured to 1G mode, LED 7 and LED8 for both boards will OFF for a second, then LED7 will LIT back. It shows that Board A has automatically switch speed to 1G and finish the auto-negotiation with Board B.


6.Type the command “TEST SFPP 100000 2” to start generates and transfers 2 bursts of 100000 packets of random sizes(up to 1518bytes) to Board A through SFP+ optical cable and it will loopback at the Avalon ST interface of Board A and received back by the internal traffic monitor module in Board B.


7. From the result shown in system console window, we can observe that all the random size packets has been received successfully by the Board B with throughput value of 0.96Gps .The design runs in 1G mode:

8. Type the command “CONFIGURE_10G” which will then write to the 1G/10G PHY IP registers, “RESET SEQ” and “SEQ Force Mode[2:0]” to reset the the sequencer , initiate PCS reconfiguration and forces the sequencer to 10G protocol:

9. Both LED 7 and LED 8 will shows LIT. Type the command “TEST SFPP 100000 2” to start generates and transfers 2 bursts of 100000 packets of random sizes(up to 1518bytes) through SPF+ module to Board A .

10. From the result shown in system console window as below, we can observe that all the random size packets has been received successfully by Board B with throughput value of 9.63Gps .The design runs in 10G mode.

11.When user hard reset the board by pressing the PB0 push button, the design will reset back to auto speed detection mode.


Appendix

Throughput calculation: Throughput = Total number of bytes data the traffic monitor received / Total cycles traffic monitor uses to receive it


a)1G mode:

Throughput

= 63920499 / 82999642

=7.70543 bytes/cycle

=7.70543 X 8Bits X 156.25MHz

= 0.96 Gbps

b)10G mode:

Throughput

= 63920499 / 8295508

=7.70543 bytes/cycle

=7.70543 X 8Bits X 156.25MHz

= 9.63 Gbps

For more detail information of the traffic controller (generator and monitor) module and the test command to program and test the device in system console, please refer to AN638, 10Gbps Ethernet MAC and XUAI PHY interoperationality Hardware Reference Design.



Disclaimer

© [2011] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.


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