In this design, we demonstrate how to configure the Stratix 10 FPGA using embedded software for the microprocessor. To illustrate the example, we use the Nios II processor as the host to perform the Stratix 10 configuration. This design is based on the Intel Stratix 10 SoC FPGA development kit. The Nios II processor that we use is programmed onto the MAX10 device on the board, in which it serves as a system controller for the development kit. Nios II reads the Stratix 10 configuration image from the flash and sends to the Stratix 10 via the AVST x16 interface. This software example is written for the Nios II processor; however, it should be portable to other microprocessor architecture by modifying the source codes.
The design example can be found on the Intel FPGA Design Store at https://fpgacloud.intel.com/devstore/platform/19.1.0/Standard/software-design-example-for-configuration-via-avalon-st-avst/
