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Source Synchronous Edge aligned input interface without using a PLL

Source Synchronous Edge aligned input interface without using a PLL



This simple example design is intended to show how to achieve timing closure for a source synchronous input interface where edge aligned data is being transmitted and there is no possibility of introducing a pll into the destination device to centre align the clock with respect to the data.

SSIP ZLP.qar

Edge Aligned SS IP with no PLL.pdf

Version history
Last update:
‎06-26-2019 06:36 PM
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