Source Synchronous Interfaces between Altera FPGAs

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Source Synchronous Interfaces between Altera FPGAs

Source Synchronous Interfaces between Altera FPGAs


Previous articles examined the methods of timing source synchronous inputs and outputs independently, when one device was an Altera® FPGA, using the Quartus® II Classic static timing analysis tool. This Tech Note examines in detail a special case when both the transmitting and receiving devices are Altera FPGAs using the new Quartus II TimeQuest static timing analysis tool. In addition to demonstrating how to do this for specific interfaces between two Altera FPGAs, information provided in the Appendices describes how to adapt this method for using on any source synchronous interface when only one side, input or output, is an Altera device.

In the first example, a 550 MHz 144-bit SDR source synchronous interface is examined as a means of passing high-throughput data between two devices. In the next example, a 400 MHz 144-bit DDR source synchronous interface is examined. The method used in these examples will maximize timing margin on the data capture and demonstrate how to time the interface for both SDR and DDR connections. No practical design could run at these internal clock speeds in an FPGA, but these examples demonstrate the speed and data width that an SDR or DDR source synchronous I/O interface is capable of running at when using Altera devices.

This article is for older generation Altera device families, the document and table could be updated for newer families.

MethodClockingDataMegaFunctionDevicesData RateMax WidthMax Throughput
High-Speed SERDESCDRSerial



Stratix GX

Stratix IIGX

400 Mbps-6,375 Gbps20128 Gbps

Stratix IIGX

Stratix GX

Cyclone II


150 Mbps-1.25 Gbps132165 Gbps
Source SynchronousSource Synchronous feedabck mode of the PLLParallel (SDR & DDR)ALTDDIOAll FPGAs

2 Mbps-550 Mbps (SDR)

4Mbps-800Mbps (DDR)

144115 Gbps

                                           Table 1. Comparison of High-Throughput Data Transfer Methods


Implementing_a_Source_Synchronous_Interface_v2.0.doc - document article for this topic, includes many figures and examples

Letzte Aktualisierung:
‎06-26-2019 06:37 PM
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