The SPI core by Altera can be confusing to get started with. This page is just to make it easier for others who follow in my footsteps. Feel free to add to the page.
For starters. The SPI core HAL is for the Master only. For Slave, you have the IRQ and you have to read the register directly. There is a limitation of 8 bit data transfers. There are workarounds for the limitation. I'll update as I go and face them.
For starters. The following basic code is sufficient.
The QSys system contains a NIOS CPU and two SPI cores. One as a Master. One as a Slave. Connected in a loopback configuration.
* SPI Test code.
* License. Do whatever you want with the code. Just remember my name :)
* Author : Zubair Lutfullah Kakakhel. But most of this comes from scattered forum posts..
* Email : EL12ZLK@LEEDS.AC.UK
//This is the ISR that runs when the SPI Slave receives data