Stratix 10 HBM2

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Stratix 10 HBM2

Contents

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• 1 Note : Following changes not required with Quartus 17.1 Release
• 2 Introduction
• 3 Generating HBM2 IP
• 4 Supporting Sequential Transactions
• 4.1 Download files
• 4.2 Simulation of Sequential Transactions

Note : Following changes not required with Quartus 17.1 Release

Quartus Prime Pro 17.1 supports sequential traffic as default and hence the following changes are not needed. 

Introduction

High Bandwidth Memory (HBM) is a JEDEC specification (JESD-235) for a wide, high bandwidth memory device. The next generation of High Bandwidth Memory, HBM2, is defined in JEDEC specification JESD-235A. The HBM2 implementation in Stratix 10 MX devices is compliant to JESD-235A. The High Bandwidth Memory DRAM is tightly coupled to the host die with a distributed interface. The interface is divided into 8 independent channels, each completely independent of one another. Each channel interface maintains a 128-bit data bus, operating at DDR data rates. 

Stratix 10 MX incorporates a high-performance FPGA fabric along with a HBM2 DRAM in a single package. Stratix 10 MX devices support upto a maximum of 2 HBM2 interfaces. Stratix 10 MX incorporates Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology to implement a silicon bridge between HBM2 DRAM memory and the Universal Interface Block (UIB), which provides physical layer and I/O buffer capabilities as well as the HBM2 controller.

Generating HBM2 IP

The Quartus prime Pro 17.1 Version supports the generation of the HBM2 IP. Simulation and synthesis of the IP are also supported.

Supporting Sequential Transactions

The Default Traffic Driver provided in the Quartus 17.1 Version provides a combination of several WR/RD transactions, including single, multiple, sequential block transactions as well as random transactions to the HBM2 memory. This can cause the efficiency shown in simulation to be lower than expected. The attached changes force the command statemachine in the Traffic Generator to issue only Sequential Transactions.

RTL Modifications Two files require modifications, they are

• altera_hbm_tg_axi_rw_stage.sv and 
• altera_hbm_tg_axi_bringup_dcb.sv.

The two attached files need to replace the existing files in the following directory:

<project_name>/hbm_0_example_design/sim/ip/ed_synth/ed_synth_tg0_0/altera_hbm_tg_axi_171/sim and 

<project_name>/hbm_0_example_design/sim/ip/ed_synth/ed_synth_tg0_1/altera_hbm_tg_axi_171/sim

Download files

The updated altera_hbm_tg_axi_rw_stage.sv and altera_hbm_tg_axi_bringup_dcb.sv files are available here for download: Media:HBM2_RTL_Seq_workaround.zip

Simulation of Sequential Transactions

The following Controller and Diagnostics Options are required as part of simulating the sequential accesses.

Controller Configurations:

• Disable Reorder buffer

Diagnostics Options:

• Run the default Traffic pattern
• Force traffic generator to issue traffic with different read/write IDs 
• Enable Efficiency Test Mode