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Stratix III 3Sl150 dev Nios II Standard Update

Stratix III 3Sl150 dev Nios II Standard Update



The StratixIII_3sl150_dev_niosII_standard design has an issue with the flash.

The flash that is used on the board is 2 die in one package. In this reference design two seperate but consecutive flash parts were instantiated in the SOPC Builder project. This only works if the CS_n are anded together becuase the physical flash part has only one chip select. The verilog is here.

 assign flash_cen = flash_select_n & flash_1_select_n;

This works fine the problem was the MSbit of the address was done incorrectly so both flash pieces in the SOPC Builder ended up selecting the same segment of memory. In this example deisng the 2 flash component were set to 0x04000000 and 0x06000000 they both have a span of 0x02000000, So they could look like one continuous part. The problem is this flash part needs 25 address short addresses. SOPC builder gives 25 bytes address and 2 chip selects for the memory. So we are missing an upper address bit. The code looks like

 assign fsm_a[24:0] = fsm_a_alignment[25:1]; //The address A0 on the flash ssram buss is dropped because the flash is 16bit and the ssram is 32bit

fsm_a_alignment comes from the SOPC Builder system and is defined [24:0]. There are two ways to correct his problem. The first is to change the SOPC Builder project to contain only 1 flash and make it 2x the size of the current one. The top level .v file would also need to be changed to accomodate only 1 flash. The second option is to leve the sopcbuilder system alone and make an additional address bit out of chip select for the secon flash instance. This is what was done here.

 assign fsm_a[24:0] = {!flash_1_select_n,fsm_a_alignment[24:1]}; //The address A0 on the flash ssram buss is dropped because the flash is 16bit and the ssram is 32bit

 

The original files are located on the altera web site http://www.altera.com/products/devkits/altera/kit-siii-host.html

The only change made here is to update the top level verilog with the fix noted above.

This 2 die flash does cause issues with Nios2-flash-programmer. When it reads the CFI tabel it reports that it only contains 1/2 of the total flash amount. This is because the flash contain 2 identical dies. And the one die does not know the other exists. So seperating the flash into two pieces in the sopc_builder makes sence.   However in 9.1 the flash programmer default override file, contians overrides for this flash, and it coerces the flash programmer to believe that the flash is 2x the size. That is fine except this breaks things like the cyclone 3c25 where only the one die is used but the flash programmer now believes it is still twice as big so it give errors like the flash is not on the correct boundary and will refuse to program the device. To overcome this you can include your own overide file which does nothing. I have inluced and example of the over ride file below for reference. From the command line the command looks like this.

%SOPC_KIT_NIOS2%\bin\nios2-flash-programmer --override=flash_override.txt --base=0x06000000 --program bootrom.srec

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Last update:
‎06-26-2019 06:45 PM
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