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Stratix V 10G Ethernet and 10G Base R PHY Interoperability Hardware Demo Design

Stratix V 10G Ethernet and 10G Base R PHY Interoperability Hardware Demonstration Design

 Last Major Update 

October 8, 2012


Altera Stratix V® 10G Ethernet Interoperability Hardware Demonstration Design. This reference design demonstrates the operation of the Altera® 10-Gbps Ethernet (10GbE) MAC and the 10G Base-R PHY IP components together and their interoperability on SFI interface with a optical SFP+ running at 10.3125Gbps. This design is built on a Transceiver Signal Integrity Development Kit using Stratix® V GX device with Altera development tool ACDS release 12.0. The designs provides a flexible test and demonstration platform on which you can control, test, and monitor 10GbE operations using system loopbacks at various points in the data path. The loopback points include XGMII interface and serial-PMA interfaces within FPGA, and external optical loopback at the SFP+ modules. This hardware demonstration reference design offers the following features: 

• Stand-alone and easy-to-use reference design example with flexibility to support two-system interoperability in various configurations. Supports 10GbE operations in 10G Base R mode using Altera 10G Base-R PHY IP. 

• Supports testing using sequence random bursts such that each burst can be configured for the number of packets, payload-data type, and size of payload. The payload data type can be either a fixed incremental value or a random sequence generated by a PRBS generator. 

• Provides packet statistics for Generator, monitor, Mac Tx, and MAC Rx. 

• Provides packet classification of frames of different sizes transmitted and received by the MAC. 

• Provides the through-put for the traffic received by the monitor. 

• System console and TCL based flexible, reusable, and extendable user control interface. This interface allows users to dynamically configure and monitor any user register(s) or parameter(s) provided by the demo hardware and various IP sub-modules used within this.

Figure below shows the block diagram overview of the 10G Ethernet Interoperability hardware demostration design for 10G Base R.


Quick Start Guide

Regenerating and Recompiling the Reference Design

You can reproduce the reference design at various levels of the development flow. A quick regeneration of a SRAM Object File (.sof) requires recompilation and regeneration of the files provided with the download.

The following sections provide guidelines for regeneration and simulation of the Altera 10GBASE-R Ethernet subsystem. 

 Generating the Altera 10G Ethernet Subsystem

To generate the Altera 10G Ethernet subsystem, follow these steps:

1. Download and unzip the reference design folder: 

         a. File:SVGX ETH 10GBASER DEMO DESIGN.qar for Quartus II 12.0

2. Start the Windows/Linux Quartus II 12.0 software. In the 10GETH_10GBASER_DEMO_DESIGN directory, open CHIP.qpf. 

3. On the Tools menu, click on Qsys. 

4. On the File menu, click Open. 

5. In the ETH10G_TOP directory, open ETH10G_TOP.qsys.

6. In the System Contents tab, double click ETH10G_TOP. The Altera Ethernet 10G Design Example dialog box appears.

7. In the CONFIGURATION tab, select MDIO, 10G Base-R PHY and Avalon-ST Single Clock Fifo.

8. In the MAC tab, at Resource Optimization Options, tick Supplementary Address, CRC on Transmit Path and Statistic Collection.

9. At the Statistic Counters pulldown menu, select Memory-based. Other options, leave them untick.

10. In the MDC tab, key in 64 in MDC DIVISOR box.

11. In the SC FIFO tab, at both Tx and Rx Single Clock Fifo, tick USE STORE AND FORWARD. Select 512 at both Fifo Depth pulldown menu. Other options, leave them untick.

12. Skip DC FIFO and XAUI PHY tabs

13. In the 10G Base-R tab, below is the recommended analog setting for the Transceiver Signal Integrity Development board. Please take note that this setting could be vary base on board to board basis.

       a. Transmitter termination resistance: OCT_100_OHMS

       b. Pre-emphasis pre-tap setting: 0

       c. Pre-emphasis pre-tap polarity setting : untick

       d. Pre-emphasis first post-tap setting: 15

       e. Pre-emphasis second post-tap setting: 0

       f. Pre-emphasis second post-tap polarity setting: untick

       g. Transmitter VOD control setting: 7

       h. Receiver Termination resistance: OCT_100_OHMS

       i. Receiver DC gain: 0

       j. Receiver static equalizer setting: 0

14. Click Finish.

15. Go to Generation tab. At the Create simulation model pull down menu, select Verilog. At Synthesis, ensure that Create HDL design for synthesis is tick.

16. Click Generate to generate ETH10G_TOP.v along with other files necessary for the simulation and hardware compilation of the design.

 Running Simulation on the Altera 10G BASE-R Ethernet Subsystem Reference Design

To run simulation on the Altera 10G BASE-R Ethernet subsystem, follow these steps:

1. Start the ModelSim-Altera 10.0d simulator software.


3. In the Tcl Console window, type the command as shown below:

do compile.tcl

4. At the end of the simulation, the ModelSim-Altera simulator provides a summary of total number of packets received. CRC errors will appear when the simulation fails. 


 Recompiling the Design

To recompile the design, follow these steps: 

       1.Start the Quartus II 12.0 software and open CHIP.qpf. 

       2.The reference design comes with the SDC constraints file to ensure the design is properly constraints. 

       3.On the Processing menu, click Start Compilation. The Quartus II software generates a .sof after the compilation.

Using the Reference Design:

This section describes the required hardware and software setup.

To run the reference design, you need the following:

Hardware Requirement: 

• Stratix V GX Transceiver Signal Integrity Development Kit  

• Finisar 10G Base R SFP+ (FTLX8571D3BCV) Optical Module 

• LC Loopback Optical Patch Cords 

• SFP+ Loopback Module 

• 644.53125Mhz Reference Clock Source

Software Requirement: 

• Altera Complete Design Suite (ACDS) 12.0 

• Quartus II 

• Qsys 

• System Console with TCL Scripting 

• ModelSim-Altera 10.0d  


 The reference design consists of two parts:

• SVGX Transceiver Signal Integrity development kit Hardware setup 

• Windows or Linux based System Console Terminal setup

The relevant setup for each of these components are provided as the following:

SVGX Transceiver Signal Integrity Development Kit Hardware setup


The SV GX Transceiver Signal Integrity Development board is shown in figure above with the hardware usage labels:

1. User need to connect the power adaptor and power on the board by switch on the SW1.

2. Connect the JTAG USB Cable to CN1.

3. User can insert the SFP+ module in to SFP+ port (J51).

       a. Insert the SFP+ loopback module.

       b. Insert the Finisar SFP+ (FTLX8571D3BCV) Optical Module with LC Loopback Optical Patch Cords.

4. Supply 644.53125Mhz LVDS Clock to the transceiver reference clock pin. You must supply this clock for Altera’s 10G Base-R PHY IP.

       a. User can use the on-board 644.53125Mhz LVDS clock. User must set the DIP switch (SW6) setting to select CLK source from on-board oscillator. 

       b. User can supply the clock from external clock generator. User must set the DIP switch (SW6) setting to select CLK source from External Clock Input (J79 and J80). 

5. The three push buttons in the figure above are used as below:

       a. PB0 - Altera 10G Ethernet System Reset.

       b. PB1 - SFP+ Tx Disable.

       c. PB2 - Stop button to abort the test due to any reason the user wants to. 

6. The two bits DIP switch setting is used to select different type of status display on the LED Host Display. User can leave if as default.

7. The LED Host Display is to show the test status: Progress, Pass, or Fail status during and after the test has been completed. 


Windows or Linux based System Console Terminal setup

Setting up Terminal to program the device and run test

Now connect the SVGX Transceiver SI dev kit using a USB blaster cable in addition to the power supply. We are using windows based example here. The Linux based test is similar to this, as basically the nios2 shell will be replaced by a Linux shell. Please follow the following steps to install and setup the files necessary to program the board. 

1. Save the zip file in your work area and unzip the directory

2. Open a nios2-eds shell

3. Change directory to ETH_10GBASER_DEMO_DESIGN

4. Type nios2-configure-sof CHIP.sof and enter. You can also chose to program it using Quartus or independent programmer. If due to some reason this sof file is corrupt and you want to regenerate it in your system you can do it by following the steps provided in the following chapters.

5. Go to the DEMO directory.

6. Type system-console and enter. It will bring up a window that has 4 sub-windows. Unlock the right bottom window and minimize all other windows.

7. The system console window looks like a command shell window with a % command prompt. Make sure you are in the DEMO directory then type: 

             source demo.tcl 

then press Enter. 

8. A Command List as shown in figure below will be shown and user can key in difference command for loopback test, changing the test parameter, and memory map display.


9. Now the setup is ready to run your test. Using various options provided in the system controller and user interface of chapter 1, you can run tests in different loopback mode by entering the loopback point such as XGMII, ALTPMA, or SFPP. 

For example: 

         TEST SFPP 20000 5

        o Please take note the command are all case sensitive. We use upper letter for all the command and parameter

        o Runs a test by sending 5 bursts of sizes 20000, 40000, 60000, and 80000 packets of random size (up to 1518 bytes) and random payload contents through MAC and loops them back on LC optical loopback patch cord. These bursts are received by the monitor after being forwarded by the 10G MAC. All the test parameter can be change using the SET_PARAM command.

10. At the end of the test, the result is display on the system console terminal and a LOG file is created. Please go through the log file to make sure NO BAD packets have been received by the Monitor. In addition this log file also provides the packet classification and statistics done by the Rx MAC. 


© [2012] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.

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