The design uses CLKIN_50, pin AN6, on the devkit, which is a 50 MHz clock. To enable CRC_ERROR detection within Quartus click on Assignments, Device. Next click on Device and Pin Options and go into the “Error Detection CRC” section, make the following selections:
To program the design into the Stratix V PCIe devkit you can use “Auto Detect” to propagate the device list and then click on the 5SGXEA7K2F40 FPGA and select “Change File …”, point to the ./output_files/sfl_top.sof file. Click on “Start”.
You can verify the FPGA is programmed when LED0 (green) is blinking a twice the rate of LED1 (red) and the Progress is 100%.
A JAM file was created called inject.jam. This is based on Example 4 on pg. 21 of AN 539. The quotations used in the example will cause an “illegal symbol name” error unless you replace them. The inject.jam file already has these corrections, also STATE IDLE should be STATE IDLE;
Make sure the Quartus bin directory is in your path (/altera/13.0sp1/quartus/bin64/), open “Command” in windows and type the following command: “quartus_jli -c 1 -a error_inject inject.jam”. You should see the following result or something similar and the CRC_ERROR pin should go high. It this example it stays high for about 10 us and repeats this every 100 ms or so. If you have Internal Scrubing Enabled it will only pulse high once.
Below is a scope capture of the CRC_ERROR pin on the Stratix V GX PCIe Devkit. This signal is on pin AN33 which is used on the devkit for PCIE_SMBCLK. This is pin B5 on the PCIe edge connector so you should not have this card plugged into a PCIe slot for this experiment.
To clear the fault enable register you should run the clear.jam file. This is copied Example 5 on pg. 23 of the document. To execute this type the following command: “quartus_jli –c 1 –a error_inject_disable clear.jam” you should see the following results in the command prompt and the CRC_ERROR pin will no longer go high.