This article introduces a new solution for the Stratix V PCIe Gen3 x8 32-bit PIPE simulation that can be used with the Denali BFM. It first explains the current PIPE simulation with the Altera BFM using a Gen3 x8 design example and the motivation for this new solution. It then discusses this simulation solution through step-by-step instructions. This solution is applicable to other third-party BFMs.
PCI Express (PCIe) is a high performance, general purpose I/O interconnect targeting a variety of computing and communications applications. Verification of PCIe designs pre-silicon to check for compliance and interoperability is important to ensure correct functionality. PureSpec-PCIe, known as Denali, has become more and more widely used by PCIe designers and verification engineers. The current Altera PCIe PIPE simulation solution does not have the 32-bit PIPE interface exposed at the top level wrapper, which makes it difficult to work with third-party BFMs. Therefore, a new solution is required for Stratix V PCIe 32-bit PIPE simulation that works with the third-party BFMs, such as the Denali BFM.
This article uses a Stratix V Gen3 PIPE simulation design example generated from Quartus II version of 13.0sp1 to illustrate the new solution. The design example is for an endpoint design. For more detail on how to generate the current PIPE simulation design, refer to Chapter 4 Getting Started with the Gen3 PIPE Simulation of Stratix V Hard IP for PCI Express User Guide for the Avalon Streaming Interface.
The Altera Stratix V PCIe Gen3 design examples support both 32-bit and 8-bit PIPE interface. They use an 8-bit PIPE interface for Gen1 and Gen2 by default (Figure 1). The 32-bit interface for Gen3 simulation is not exposed at the top level wrapper pcie_de_gen3_x8_ast256.v. Instead, the module pipe32_hip_interface (altpcietb_pipe32_hip_interface.v) is used to connect the PCIe Hard IP lowest level wrapper altpcie_hip_256_pipen1b.v to the Altera BFM. The parameter enable_pipe32_sim_hwtcl in altpcie_sv_hip_ast_hwtcl.v is set to 1 to enable 32-bit PIPE simulation for Gen3 mode.
Figure 1. Hierarchy of Current Stratix V PIPE Simulation Design Example f/f6/Altera.PNG
Because the 32-bit PIPE interface is not exposed at the top level, this makes it difficult to connect to third-party BFMs. This article introduces a new solution that provides a standardized 32-bit PIPE interface that works with third-party BFMs.
The new solution has a Hard IP (HIP) 32-bit PIPE interface that is brought up to the top level wrapper for the endpoint (EP) and that can connect directly to third-party BFMs (Figure 2).
Figure 2. Hierarchy of Stratix V Gen3 PIPE Simulation with Denali BFM 5/50/Denali.PNG
The PCLK comes from the Denali Model and feeds the Denali Monitor and PCIe endpoint.
Perst and Npor are tied together in this case and can be driven by the user reset logic.
The goal is to create a new 32-bit PIPE interface that is exposed at top level wrapper.
Add 32-bit PIPE interface ports at each level of the hierarchy as shown below (Figure 3). The full port list can be found from here.
Figure 3. Expose 32-bit PIPE Interface at Top Level d/d0/Pipe_overview.PNG
The newly created 32-bit PIPE interface needs to be connected to the HIP model in the lowest level of the hierarchy (Figure 4). For the TX path, a set of new assignment statements are needed to hook up the interface with the HIP model by mapping the TX output signals of altpcie_hip_256_pipen1b to the corresponding TX output signals of the HIP model.
Figure 4. Connect New 32-bit PIPE Interface to HIP Model (TX Path) 2/25/Pipe_tx.PNG
For the RX path, there is a mux to select serial interface, 8-bit interface, or 32-bit interface. The mux feeds into the RX input signals of the HIP model. Replace the original 32-bit interface signals with the new 32-bit interface signals shown in red (Figure 5).
Figure 5. Connect New 32-bit PIPE Interface to HIP Model (RX Path) 5/5a/Pipe_rx.PNG
PCLK in the new solution is driven by the BFM and feeds into the HIP endpoint. Table 1 shows the different frequencies for different data rates. The existing PCLK connection to the HIP model needs to be replaced in
altpcie_hip_256_pipen1b.v (Figure 6).
Figure 6. PCLK Modification in altpcie_hip_256_pipen1b.v 3/3a/PCLK.PNG
Note pclk_in is an input clock at top level wrapper pcie_de_gen3_x8_ast256.v.
The port pllfixedclkcentral takes an input clock source and generates the PCIe HIP core clock. There are two input clock source available, 500MHz for Gen2/Gen3 configuration and 250MHz for Gen1 configuration. Connect the clk500_out to pllfixedclkcentral for your Gen3 (or Gen2) configuration (Figure 7). Note for your Gen1 simulation, you need to use clk250_out.
Figure 7. HIP Core Clock Connection in altpcie_hip_256_pipen1b.v c/ca/Pllfixedclkcentral.PNG
This article introduces a new solution for the Stratix V PCIe 32-bit PIPE simulation and provides the implementation instructions. The new solution uses a standardized 32-bit PIPE simulation interface which improves flexibility for customers using third-party BFMs, such as Denali BFM.