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Stratix V PLL Reconfiguration

Stratix V PLL Reconfiguration


Download Source & Example Project

Sv pll mif reconfig rev1.2a.zip  - 25 Aug 2013 -

... updated to allow simulation with Qsys subsystem. That is the only change from v1.2.

Sv pll mif reconfig rev1.2.zip- 18 Aug 2013 -

.. updated for 13.0SP1DP1

.. fixed bugs in altera_pll_reconfig_core.v

Sv pll mif reconfig rev1.1a.zip - 5 March 2013 -

.. fixed polarity on mgmt_reset for System Console

.. added description on using System Console to wiki text

Design Description

This design is meant to illustrate how to reconfigure a PLL without reconfiguring the FPGA. It is targeted to the Stratix V PCIe Devkit and makes use of the following Altera MegaFunctions:

The design reconfigures between two different PLL configurations. When you first program the FPGA the PLL takes an input reference of 125 MHz and outputs three clocks:

  • 37.5 MHz
  • 37.5 MHz 12% duty cycle and 90 degree phase shift
  • 37.5MHz 50% duty cycle and 90 degree phase shift

When you reconfigure the PLL it uses the MIF reconfiguration method. Meaning the entire PLL is reconfigured. After reconfiguration the output clock rate on the PLL will be 22.38 MHz.

It is recommend that you familiarize yourself with this document “Implementing Fraction PLL Reconfiguration with ALTERA_PLL and ALTERA_PLL_RECONFIG Megafunctions” http://www.altera.com/literature/an/an661.pdf This design was compiled and simulated last on 15 Feb 2013 with Quartus v12.1SP1 and Questasim v10.1c. For details on the Stratix V GX PCIe Development Kit: http://www.altera.com/literature/manual/rm_svgx_fpga_dev_board.pdf

The installation files for the development kit can be found here: ftp://ftp.altera.com/outgoing/devkit/12.0/stratixvgx_5sgxea7kf40_fpga_v12.0.0.1.exe. An update version of the install kit can be found here: (Windows) ftp://ftp.altera.com/outgoing/devkit/13.0/stratixVGX_5sgxea7kf40_fpga_v13.0.0.0.exe or here (Linux) ftp://ftp.altera.com/outgoing/devkit/13.0/stratixVGX_5sgxea7kf40_fpga_v13.0.0.0.zip

What Does This Thing Do Anyway?

This is a simple design which is meant to illustrate a method for reconfiguring a PLL in a Stratix V device. This design starts with a “default” PLL configuration, pll_inst1, and there are settings for both PLLs (MIF files) stored in two internal memory blocks in the FPGA. The image for pll_inst2 is selected as the PLL reconfiguration image once the FPGA has been initially programmed with the SOF file.

To reconfigure to the pll_inst2 settings you press USER_PB1 on the board. The button_hystersis block deglitches this input and generates a few clock cycle wide pulse. This pulse is passed into the pll_config_ctrl block on the “config_request” pin. The pll_config_ctrl control block monitors the mgmt_waitrequest signal from the pll_config_inst block. Once this signal is deasserted the pll_config_ctrl block will write two address and values on the mgmt_address and mgmt_writedata ports. First address 6’h1F is written to 32’h00000000 and then address 6’h02 is written to 32’h000000001. The first address (6’h1F) is the MIF starting address register and the second address (6’h02) is the start address register (you can write a 1 or 0 to this address). Both of these registers need to be written in order to start a MIF configuration. The mgmt_waitrequest signal is monitored and when it is deasserted the MIF configuration is complete. After this occurs the pll_config_ctrl will wait for a predetermined time and then will pulse the rst signal on the PLL. This will align the output counters of the PLL and is required for proper operation. At this point the configuration of the PLL is complete. The pll_config_ctrl also has some circuitry to reset the PLL in case it loses lock for any reason. This lock monitoring circuit will not reset the PLL during a configuration event.

There is a reset signal on the pll_reconfig_inst block, mgmt_reset. Asserting this reset will cause the PLL to go back to the default FPGA programming image, pll_inst1. This is a failsafe mechanism, if the reconfiguration goes awry this signal can be asserted to restore normal operation and allow another reconfiguration attempt. In this example design USER_PB0 is assigned this function.

When configuring to the alternate image, pll2_inst the VCO is 537.12 MHz (1.89 ns period). To get a 90 degree phase shift (11.17 ns) on outclk_1 and outclk_2, both 22.38 MHz (44.68 ns period), you need to add some phase shift to those clocks. The original PLL configuration has a VCO of 600 MHz (1.667 ns period) with a clock frequency of 37.5 MHz (26.67 ns) so a 90 degree shift is 6.67 ns. The minimum shift is 1/8 of the VCO period, ~208 ps per shift … or 32 steps. That is the setting from the main PLL. The alternate PLL minimum shift is ~236 ps ( 1/8 of the 537.12 MHz VCO) … or 47 steps. Therefore you need to add 15 phase bumps to properly align outclk_1 and outclk_2. ** A delay (64 counts of 50 MHz) was added between the two phase bump configurations. If these were phase bumps performed back to back the PLL went into an indeterminate state.

This design edits the Altera PLL Reconfiguration MegaWizard files and creates two separate memories. Another method would have been to take the two MIF files and concatenate them together. If this design had done that we could use the MIF starting address register to specify the correct offset for the image of interest.

Design Hierarchy and Pin Assignments

This is the hierarchy of the design.

f/f3/Svpll_img1.png

These are the assigned pin locations for the design.

9/93/Svpll_img2.png

Changes to Altera PLL Reconfiguration MegaFunction

To enable multiple instances of a PLL reconfiguration you can either: (1) make use of the offset address register in the Altera PLL Reconfiguration MegaFunction and store all of the images in a single MIF (2) edit the MegaFunction instance to add multiple memories which can be switched between by external control signals.

For this example I went with the second option and made some minor edits to the generated files. Please remember if you re-generate these MegaWizard files your changes will be over written. The items which were changed are commented. altera_pll_reconfig_mif_reader.v

altera_pll_reconfig_mif_reader.v

3/3e/Svpll_img3.png


altera_pll_reconfig_top.v

1/16/Svpll_img4.png

e/eb/Svpll_img5.png

pll_reconfig_inst.v

7/7e/Svpll_img6.png

Updates to PLL Reconfig, v13.0SP1DP1

A few changes were made to the altera_pll_reconfig_core.v file which is part of the altera_pll_reconfig block and generated files. In simulation and hardware various reconfigurations would result in mgmt_waitrequest being stuck at 1 and this in turn prevented further operations. This was traced down to an issue with dprio_start so this was moved to its own always construct. An additional state was added to the dprio_cur_state and dprio_next_state vectors to reset the signals and state machine after each use. You can either use this block or the original version of it, named altera_pll_reconfig_core_orig.v

Example Design Files

root directory:

button_hysteresis.v – this file processes / deglitches the push buttons on the board ddr_o.v – this is a MegaWizard created x1 DDR output pll_config_ctrl – this module handles writing to the pll_reconfig_inst block upon a button event. There is also logic present for resetting the PLL on loss of lock or after reconfiguration to align the output counters. top.v – this is the top level design file and instantiates: button_hysteresis, ddr_o, pll_config_ctrl, top.v and pll_inst1.v my_issp.v – this is an In-System Sources and Probes module, it is used to provide an alternate reset path for the PLL if needed

.\pll_files directory:

pll_inst1.v – this is the main PLL instance pll_inst2.v – this is the secondary PLL instance

This directory contains the PLL two different PLL configurations along with the MegaWizard generated outputs for simulation. Both PLLs are Fractional PLLs with a 125 MHz input clock.

pll_inst1: C0 – 37.5 MHz, no phase shift, 50% duty cycle C1 – 37.5 MHz, 90 degree phase shift, 12% duty cycle C2 – 37.5 MHz, 90 degree phase shift, 50% duty cycle

pll_inst2: C0 – 22.38 MHz, no phase shift, 50% duty cycle C1 – 22.38 MHz, 90 degree phase shift, 12% duty cycle C2 – 22.38 MHz, 90 degree phase shift, 50% duty cycle

You can view the settings for the PLL in the MegaWizard. It is required that this option be checked to allow MIF streaming.

0/0b/Svpll_img7.png

.\pll_reconfig_inst directory:

This directory contains the PLL reconfiguration logic generated by the MegaWizard. The changes to these files were described previously.

altera_pll_reconfig_core.v altera_pll_reconfig_mif_reader.v altera_pll_reconfig_top.v

Running the Simulation

There is a ./simulation folder in the 7-zip file. Within this folder there are the following files:

msim_setup.tcl – this scripts sets up the simulation environment pll_inst1.mif – this is the MIF file for pll_inst1, it was copied over from the pll_files/pll_inst1 directory pll_inst2.mif – this is the MIF file for pll_inst2, it was copied over from the pll_files/pll_inst2 directory top_tb.v – this is the top level testbench instance wave.do – this is the wave file for Questasim

The design was simulated in Questasim v10.1c.

To run the simulation:

1) Open Questasim or Modelsim. Uncomment `define SIM 1 in the top.v file.

2) Browse to the folder where you expanded the .7z file and select the ./simulation folder

3) Type “do msim_setup.tcl”

4) Type “dev_com” … this compiles the simulation libraries from Quartus

5) Type “com” … this compiles the source files

6) Type “do wave.do” … this loads the wave window with a predefined set of signals

7) Type “run –all” … this runs the simulation

A simulation screen capture is on the next page.

5/56/Svpll_img9.png

PLL State Diagram

The state diagram for the pll_config_ctrl “config_state” is shown below. I didn’t reorder the states to make them flow nice so this will map out what is going on.

d/d8/Pll_config_state_diagram.PNG

Running the Design in Hardware

Below is a picture of the board. To run the design use the .sof file in the ./output_files directory and program it into the FPGA. Once programmed you can use the buttons to switch between images. PB0 – pushing this button resets the design, it will restore the original PLL configuration because it also resets the Altera PLL Reconfiguration (pll_reconfig_inst) design using the mgmt_reset signal PB1 – pushing this button will start a PLL reconfiguration PB2 – pushing this button will change the MIF selection. A “green” LED1 will indicate the pll_inst2 (22.38MHz) image is selected. A “red” LED1 will indicate the pll_inst1 (37.5MHz) image is selected. The board starts with pll_inst1 active and pll_inst2 is the selected MIF image.

f/fe/Sv_pll_img10_update.png

Here are screen captures of the design in running on the development kit. The first picture shows the board as it comes up, note the relationship of the signals. The yellow signal is outclk_0, green outclk_1 and blue outclk_2.

8/83/Sv_pll_img11_update.png

This is after reconfiguration …

6/69/Sv_pll_img12_update.png

Using System Console

I have also embedded System Console in the design. To access the PLL reconfiguration circuitry you need to enable System Console to communicate with the PLL reconfiguration block. Below is a picture of the Qsys system and this shows the components in the system. The file is named sys_console_ctrl.qsys.

4/47/Svpll_img13_update.png

The interface to the PLL reconfiguration block starts at address 0x0 and goes to address 0x00FF. There are two PIOs, a pio_input and a pio_output. These are addressed at 0x110 – 0x11F and 0x100 – 0x10FF respectively. Finally an onchip memory is provided for simple reads and writes to verify System Console functionality.

pio_input: This is a 32 bit input PIO. I have spaced the sampled signals 3 bits apart from each other so when respresented in hexadecimal (as reads / writes through System Console are) they are easliy decoded. When you read address 0x110 through System Console you will get 8 hexadecimal characters back, e.g. 0x1000000. These 8 hexadecimal characters correspond to 8 signals, 1 indicating active.

7: locked

6: mgmt_waitrequest

5: mgmt_reset

4: pll_arst

3: pio_output[3]

2: pio_output[2]

1: pio_output[1]

0: pio_output[0]

pio_output: This is a 8 bit output PIO. Unlike the pio input I have not spaced these signals out. Here is the mapping for the 8 bits

7: Not used

6: Not used

5: Not used

4: Not used

3: System Console Control (when 1 System Console is active, when 0 push buttons are active)

2: mif_select (1 is the ~22 MHz MIF, 0 is the ~37 MHz MIF)

1: mgmt_reset

0: pll_arst

To select System Console control and the 22 MHz MIF you would write 0xC to address 0x100. To reset the PLL you would write 0x1 to address 0x100. To reset the PLL to the original configuration you could either write 0x2 to address 0x100 or in the System Console window type “source mif_reconfig_orig.tcl”.

I have included a few scripts to illustrate commands that can be issued through System Console. System Console makes use of the JTAG to Avalon Master component and as such uses byte addressing. Therefore anytime you write to an address in the PLL reconfiguration space you need to add two 0’s to the bottom. For example to write to the “Dynamic Phase Shift” register whose address is 000110 you would write to address 0x18 (or 00011000).

Three scripts are included:

mif_reconfig.tcl – this will reconfigure from the default PLL setting (~37 MHz) to the ~22MHz setting. It will also update the output phases for counter 1 and counter 2 as is done when using the push buttons. mif_reconfig_orig.tcl – this will reconfigure the PLL to the default PLL setting (~37 MHz). Alternatively you could write to address 0x100 with 0x2 to assert a mgmt_reset which will accomplish the same thing for this example. counter0_update.tcl – this will reconfigure the output counter C0 with an updated divisor, setting high count and low count to be 2.

c/c6/Svpll_img14_update.png

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Last update:
‎06-26-2019 07:03 PM
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