Community
cancel
Showing results for 
Search instead for 
Did you mean: 

Stratix V Remote Update

Stratix V Remote Update


Stratix V Remote Update Reference Design

Design Files Sv remote update rev1.0.zip

  • Based on the testing conducted in this reference design you must continually toggle the “reset_timer” signal in the application image or you will get a watch dog timer reset and will reconfigure to the “factory” image.

This is a simple design to illustrate how to implement active serial remote update in a Stratix V device. The design uses the EPCQ256 and Stratix V EP5SGXEA7K2F40C2 device on the Stratix V PCIe Development Kit: http://www.altera.com/products/devkits/altera/kit-sv-gx-host.html

Reference Manual: http://www.altera.com/literature/manual/rm_svgx_fpga_dev_board.pdf

This design also uses the ALTREMOTE_UPDATE MegaFunction, documentation link: http://www.altera.com/literature/ug/ug_altremote.pdf

There are two portions to the design, “top_bottom” and “top_top”. The “top_bottom” design is essentially the factory image. This is the image that will initate configuration to the application image, “top_top”. The designs were named this way because “top_bottom” occupies Page_0 at starting address 0x0 in the EPCQ256 flash. The “top_top” design occupies Page_1 at starting address 0x01000000 in the EPCQ256 flash.

The main clock used in this design is “clk” which is a 1.8V 50 MHz clock that comes into pin AN6 on the Stratix V device. This clock is divided by 8, 6.25 MHz, to be used by the ALTREMOTE_UPDATE block. It is recommended the clock feeding the remote update block be less than 10 MHz.

top_bottom Design Description

When this design first configures into the devkit red led 0 will light. Green led 2 will light when the state machine is in state 4’b0111.

This design consists of the remote update block, some LED status signals and a simple state machine. Upon power-up / FPGA configuration this image is loaded into the FPGA. Here is a list of the writes performed to the remote update block. Each write command below consists of first setting up the address and data, then asserting the write signal for one clock cycle. This is followed by a brief wait ( 8 clock cycles) prior to starting the next write.

  1. param is set to 3’b100 (set flash address). data_in is set to 24’h010000. The lower 8-address bits are truncated from flash address, 0x01000000. This is documented in the following online solution, refer to the endnote for details.
  2. param is set to 3’b101 (configuration mode). data_in is set to 24’h000001. This sets the AnF bit as directed in the user guide for the application image.
  3. param is set to 3’b010 (watch dog timer value). data_in is set to 24’h000FFF. This sets the watch dog counter timer to its maximum 12 bit value.
  4. param is set to 3’b011 (watch dog time enable). data_in is set to 24’h000001. This enables the watch dog timer.

Once these commands are written one of two things will happen. If you have RECONFIG_VIA_STATE defined at the top of the file the state machine will assert “reconfig” on the ALTREMOTE_UPDATE block in the design. If this is not defined you will need to actuate PB0 on the board to initiate a reconfiguration. By default the RECONFIG_VIA_STATE is not defined.

In the 4’b0111 state without RECONFIG_VIA_STATE defined it will continually read from param 3’b000 which is the status of the reconfiguration. Should configuration to the application image fail a led status will light on the user red leds as follows:

  • Red led 7 – wdtimer source
  • Red led 6 – nconfig source
  • Red led 5 – runconfig source
  • Red led 4 – nstatus source
  • Red led 3 – crcerror source

top_bottom state diagram

3/38/Svremote_img1.png

top_top Design Description

9/99/Svremote_img2.png

This contains a modified remote update block which is read only. When the FPGA is configured with this image green led 0 will light and red led 0 will flash once per second. Red led 3, 2 and 1 will show the status of user switch 2, 1 and 0 respectively. When the dipswitch is at 0 the led will be lit.

Depending on the selection of the dipswitch the reset condition of the “reset” and “reset_timer” signals will be different. This is shown in the top_top Design Waveform sections With dipsw1 and dipsw0 set respectively:

  • 2’b00 or 2’b11: reset and reset_timer will toggle between 0 and 1
  • 2’b01: reset and reset_timer will start at 0, go to 1 and then stay at 0
  • 2’b10: reset and reset_timer will start at 0, go to 1 and stay at 1

dipsw2 controls whether or not “reset” is ever allowed to go to 1. If dipsw2 is “1”, red led 3 will be off and “reset” will always be “0”. Otherwise reset will act as it does as indicated above and as shown in the diagrams.

top_top State Diagrams

7/74/Svremote_img3.png

top_top Design Waveforms

4/4c/Svremote_img4.png

With dipsw1 and dipsw0 at 2’b00 or 2’b11, respectively


This testing was done to understand the interface, toggling reset_timer is what needs to be done to reset the watchdog timer. With dipsw2 at 1’b1 and dipsw1 and dipsw0 at 2’00 or 2’b11, respectively

a/a1/Svremote_img5.png

With dipsw1 and dispsw0 at 2’b01, respectively

9/97/Svremote_img6.png

With dispsw1 and dipsw0 at 2’b10, respectively

7/7e/Svremote_img7.png

Convert Programming Files

To create a JIC to program into the EPCQ256 device via the JTAG connection on the Stratix V you will need to use the Convert Programming Files in Quartus. This is under File, and Convert Programming Files in Quartus. Note the starting address for the different pages and each SOF is compressed (right click on the SOF file and click on Properties to get to that option).


End Notes

How can I write the application image boot address into the data_in[23..0] port in the altremote_update for Arria V, Cyclone V and Stratix V devices to address the entire memory space in an EPCQ256 device? Description Arria® V, Cyclone® V and Stratix® V devices remote update circuitry can only handle 24-bit addressing. For configuration devices such EPCS128 or EPCQ128 and smaller density configuration devices using 24-bit addressing, the 24-bit PGM[23:0] field corresponds to all 24 bits of the active serial starting address. However for EPCQ256 devices that use 32-bit addressing, the PGM[23:0] field corresponds to the 24 MSB of the active serial starting address. Thus the 32-bit address would be {pgm[23:0], 8’b0}. Workaround / Fix In the altremote_update module for EPCQ256 devices, you will need to truncate the lowest 8 LSB when writing the application image boot address during factory image. For example if the boot address is 0x00020000, then you need to set the 0x000200 into data_in[23..0] of the megafunction. For example if the boot address is 0x01C00000, then you need to set the 0x01C000 into data_in[23..0] of the megafunction.

  • ii There is a documentation error on pg. 35 of the Stratix V PCI reference manual. USER_PB0 is defined as pin C7, which is actually USER_PB2. The correct pin number is A7 and this is correct in the schematics.
Attachments
Version history
Revision #:
1 of 1
Last update:
‎06-26-2019 07:06 PM
Updated by:
 
Contributors