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Stratix V Six Dual Rank DDR3 SDRAM UniPHY 666MHz Quarter Rate

Stratix V Six Dual Rank DDR3 SDRAM UniPHY 666MHz Quarter Rate



 Last Major Update

May 2013 – using Quartus II v13.0


Design Overview

This example design uses Stratix V to instantiate six x72 DDR3 dual rank DIMMs configured at 667MHz. 

 

Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
Quartus versionQuartusII v13.0 / v13.1
FPGA5SGXEABN1F45C2
Kit-
Memory deviceDDR3 SDRAM
Memory speed800MHz
Memory topologyx72-bit dual rank, 4 DDR3 SDRAM components 
IP usedUniPHY

 

How the design was created

The UniPHY megawizard was used to create a x72 DDR3 Master (PLL/DLL/OCT) with two slaves. The example design that is auto created instantiates the 1st slave but the 2nd slave has to be added manually. These three interfaces are placed along one side of the device and then the whole block duplicate on the other side to provide six interfaces in two groups of three (master + 2 slaves). A sdc script (altera.sdc) was added to modify some clock delays to assist in closing timing.

 

A Quartus archive for the final project is also included for reference.

The Quartus Archive file for this design is located here


Update History

Page Creation – May 2013 – Stratix V Dual Rank DDR3 SDRAM UniPHY 666MHz Quarter Rate, Quartus II v13.0 using UniPHY. 

 

See Also

1. List of designs using Altera External Memory IP 


External Links

1. Altera's External Memory Interface Solutions Center 

2. Altera's External Memory Interface Handbook 

 

Key Words

UniPHY, DDR3 SDRAM, Design Example, External Memory , Stratix V, SV



 

Version history
Revision #:
1 of 1
Last update:
‎06-26-2019 07:06 PM
Updated by:
 
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