Community
cancel
Showing results for 
Search instead for 
Did you mean: 

Stratix V Transceiver PHY Basic Design Examples

Stratix V Transceiver PHY Basic Design Examples



Stratix V TX PLLs merging in Native PHY instances with TX PLL dynamic reconfiguration enabled design example

Overview

This basic design example with demonstrates how to merge the TX PLLs of two Stratix V Native PHY instances with TX PLL reconfiguration enabled by using the TX PLL reconfiguration group assignment. By default, when the TX PLL dynamic reconfiguration is enabled, Quartus will instantiate separate TX PLLs for the Native PHY instances even though both transceiver configurations can actually share a single TX PLL. With the TX PLL reconfiguration group assignment, user can specify to Quartus the specific TX PLLs to merge to save the TX PLL resources on the device. In this design, the ATX PLL is used and the reconfiguration group setting has been pre-assigned. You can refer to the assignment example in the Assignment Editor.

To enable merging of the ATX PLLs in Native PHY instances with PLL reconfiguration enabled, do the following steps:

1. Extract the project QAR 

2. Run Analysis & Synthesis compilation 

3. Open up RTL Viewer 

4. Look for the lowest level ATX PLL node for the first instance of Native PHY in RTL viewer 

5. Right click on the ATX PLL and locate the node in Assignment Editor 

6. Populate the ATX PLL node into the "To" column of Assignment Editor 

7. Select Assignment Name = XCVR TX PLL Reconfiguration Group Setting 

8. At the "Value" column, set the group number as “5” for example 

9. Repeat steps 4-8 and set the same group number as “5” for the ATX PLL of the other Native PHY instance 

10. Save and compile the design 

11. Check the Fitter report -> GXB Reports -> Transmitter PLL 

12. You should see that there is only one ATX PLL resource used which indicate the TX PLLs for the two Native PHY instances have been successfully merged 

Design File

Stratix V ATX PLLs merging in Native PHY instances with TX PLL dynamic reconfiguration enabled desig...

Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
DeviceStratix V GX
Quartus versionQuartus Prime v15.1
Datarate2Gbps
Number of channels2
IP usedNative PHY IP, Transceiver Reconfiguration Controller, Transceiver PHY Reset Controller


Version history
Revision #:
1 of 1
Last update:
‎06-26-2019 07:07 PM
Updated by:
 
Contributors