Stratix10 Transceiver PHY Basic Design Examples
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Stratix10 Transceiver PHY Basic Design Examples
Stratix 10 GX Dynamic Serial and Post CDR Loopback Modes Design Example
Overview
This design example is to demonstrate dynamic enabling and disabling of serial and post CDR loopback modes in the Stratix 10 transceiver using direct reconfiguration flow. The simulation example will use a link test between two transceiver channels to demonstrate the different behaviours at the RX parallel data outputs with different loopback modes. By default, the connection of the two transceiver channels are as following:
1. 0xBC -> TX1 -> RX0
2. 0xCC -> TX0 -> RX1
With serial loopback enabled at CH0, parallel data of 0xCC (probably with different word boundary) will be observed at RX0. With post CDR reverse serial loopback enabled at CH0, parallel data of 0xBC (probably with different word boundary) will be observed at RX1.
To run the simulation, do the following:
1. Unzip the files
2. Change the Modelsim directory to the unzipped folder
3. Type "source simulation_setup_top.tcl"
4. Type "ld" to compile
5. Type "simulate" to start simulation
Design File
Stratix 10 GX Dynamic Serial and Post CDR Loopback Modes Design Example Q18.0 (ZIP)
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Stratix 10 GX |
| Quartus version | Quartus Prime 18.0 |
| Modelsim version | ModelSim - Intel FPGA EDITION 10.6c |
| Datarate | 1.25Gbps |
| Data pattern | Fixed |
| Number of channels | 2 |
| IP used | Native PHY IP, ATX PLL, Transceiver PHY Reset Controller |
Stratix 10 TX PAM4 SMA Loopback with TTK Design Example
Overview
This design example is to demonstrate two PAM4 XCVR channels running at 51.6Gbps. This design has transceiver toolkit enabled and also come with SignalTap for basic status monitoring. With the Transceiver toolkit, it allows you to perform auto sweep to find the optimal analog settings for a specific board setup. You can then port the optimal settings found back to your own design and further fine tune from there. You may further customize the SignalTap to monitor signals of your interest. This design has been tested on Intel® Stratix® 10 TX Signal Integrity Development Kit with SMA loopback.
After downloading the SOF file, you may launch the Transceiver Toolkit at the Quartus® Prime -> Tools -> System Debugging Tools -> Transceiver Toolkit. Then load the design into Transceiver Toolkit and the transceiver channel should be auto-populated in the Transceiver Toolkit.
Design File
Stratix 10 TX PAM4 SMA Loopback with TTK Design Example Q18.1 (QAR)
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Stratix 10 TX |
| Quartus version | Quartus Prime Pro 18.1 |
| Datarate | 51Gbps |
| Data pattern | Incremental |
| Number of channels | 2 |
| IP used | S10 E-Tile Transceiver Native PHY IP, In-System Sources & Probes Intel FPGA IP |
Stratix 10 H-Tile Transceiver with Transceiver Toolkit Design Example
Overview
This basic design example demonstrates one H-Tile transceiver channel link which can work with the transceiver toolkit in Intel® Stratix® 10 device. With the transceiver toolkit, it allows you to perform auto sweep to find the optimal analog settings for a specific board setup. You can then port the optimal settings found back to your own design and further fine tune from there. This design has been tested with H-Tile channel on Intel Stratix 10 TX Signal Integrity Development Kit with internal serial loopback from transceiver toolkit. You may customize the design to your targeted pinout
After downloading the SOF file, you may launch the Transceiver Toolkit at the Quartus® Prime -> Tools -> System Debugging Tools -> Transceiver Toolkit. Then load the design into Transceiver Toolkit and the transceiver channel should be auto-populated in the Transceiver Toolkit.
Design File
Stratix 10 H-Tile Transceiver with Transceiver Toolkit Design Example Q18.1 (QAR)
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Stratix 10 TX |
| Quartus version | Quartus Prime Pro 18.1 |
| Datarate | 3072Mbps |
| Data pattern | Fixed |
| Number of channels | 1 |
| IP used | Stratix 10 L-Tile/H-Tile Transceiver Native PHY IP, ATX PLL, Transceiver PHY Reset Controller, In-System Sources & Probes Intel FPGA IP |
Stratix 10 TX PAM4 and NRZ with QSFPDD interfaces and Transceiver Toolkit Design Examples
Overview
The design examples are to demonstrate PAM4 and NRZ XCVR channels interface with QSFPDD modules running at 51Gbps and 28Gbps. There are 3 variants of design example:
1. Stratix 10 TX PAM4 8 x 51Gbps with QSFPDD 1x1 interface 2. Stratix 10 TX NRZ 16 x 28Gbps with QSFPDD 1x2 interface 2. Stratix 10 TX NRZ 16 x 28Gbps with QSFPDD 2x1 interface
These designs have transceiver toolkit enabled for BER testing. These designs have been tested on Intel® Stratix® 10 TX Signal Integrity Development Kit with different QSFPDD interfaces. After plugging in the QSFPDD loopback modules to the respective QSFPDD cages and downloading the SOF files, you may launch the Transceiver Toolkit at the Quartus® Prime -> Tools -> System Debugging Tools -> Transceiver Toolkit. You may then use toolkit to monitor the link status as well as perform BER tests.
Design File
Stratix 10 TX NRZ 16 x 28Gbps with QSFPDD 1x2 interface Q18.1 (QAR)
Stratix 10 TX NRZ 16 x 28Gbps with QSFPDD 2x1 interface Q18.1 (QAR)
Stratix 10 TX PAM4 Loopback Simulation Design Example Q18.1 (QAR)
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Stratix 10 TX |
| Quartus version | Quartus Prime Pro 18.1 |
| Datarate | 51Gbps, 28Gbps |
| Data pattern | Fixed |
| Number of channels | 8, 16 |
| IP used | S10 E-Tile Transceiver Native PHY IP, In-System Sources & Probes Intel FPGA IP |
Stratix 10 TX PAM4 Loopback Simulation Design Example
Overview
This design example is to demonstrate how to perform Modelsim loopback simulation with 2 PAM4 XCVR channels running at 51Gbps. Note that you would need to run the simulation up to 400us before checking on the simulation results.
To run the simulation, do the following:
1. Extract the files
2. Change the Modelsim directory to the native0\sim\mentor folder
3. Type "source msim_setup.tcl"
4. Type "ld" to compile
5. Type "simulate" to start simulation
Design File
Stratix 10 TX PAM4 Loopback Simulation Design Example Q18.1 (QAR)
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Stratix 10 TX |
| Quartus version | Quartus Prime Pro 18.1 |
| Modelsim version | ModelSim - Intel FPGA EDITION 10.6d |
| Datarate | 51Gbps |
| Data pattern | Fixed |
| Number of channels | 2 |
| IP used | S10 E-Tile Transceiver Native PHY IP |
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