Figure 1 illustrates an Altera Arria® 10 FPGA SyncE reference design that consists of multiple 1G/10Gb Ethernet MAC and PCS+PMA (PHY) IP instances. These PHY IP cores recover the receiver (RX) clocks from their respective 1G/10Gbps Ethernet ports. The reference design selects one clock as a master system clock based on the SyncE management software control and outputs it to an FPGA output. The FPGA core is filled with instances of a digital noise-maker design to create a real world scenario for measuring the clock parameters.
This design has been tested with external SyncE standard-compliant PLLs from two different vendors i.e. Silicon Labs (Si5345) and Integrated Device Technology (82P33831). Link for related white papers are given at the bottom of this page.
The ITU-T G.8262 SyncE standard-compliant PLL attenuates the selected clock signal’s wander and jitter to within the SyncE specification, and then this stabilized clock is used to feed the FPGA’s serial transmitter (TX) PLL in sync with the master Ethernet port’s clock frequency to realize a complete synchronization loop. This reference design can support four reconfigurable serial transceiver channels in SyncE mode at 1 Gbps or 10 Gbps line rate using Altera’s Arria10 (10AX115S4F45I3SG) GX FPGA Transceiver Signal Integrity Development Kit (https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-a10-gx-si.html). The design can be modified to support to 40Gb and 100Gb Ethernet MAC and PHY IP and clocks as well.
Port list of reference design:
1. Four TX channels:
ch0_tx_serial_data (J31, J33)
ch1_tx_serial_data (J35, J37)
ch2_tx_serial_data (J39, J41)
ch3_tx_serial_data (J43, J45)
2. Four RX channels:
ch0_rx_serial_data (J30, J32)
ch1_rx_serial_data (J34, J36)
ch2_rx_serial_data (J38, J40)
ch3_rx_serial_data (J42, J44)
Source: SMA connector J53 & J54 for external reference clock.
Source: SMA connector J56 & J57 for external reference clock.
Source: Dedicated onboard clock
Name: user_pushbutton0, S1
7. usr_seq_reset_pb3: Resets the sequencer and initiates PCS reconfiguration for channels 0 & 1.
Name: user_pushbutton3, S4
8. usr_seq_reset_pb2: Resets the sequencer and initiates PCS reconfiguration for channels 2 & 3.
Name: user_pushbutton2, S3
9. sync_eth_rx_clkout: clock output to the external syncE PLL.
Source: J51 & J52
10. user_led0: Blinks if phy_mgmt_clk is present.
Name: user_led0, D13
11. user_led2: Blinks if pll_ref_clk_1g is present.
Name: user_led2, D15
12. user_led4: Blinks if xgmii_rx_clk is present.
Name: user_led4, D17
To recompile the design, follow these steps:
Start the Quartus Prime 15.1 software and open de_wrapper.qpf.
The reference design comes with the SDC constraints file to ensure the design is properly constraints.
On the Processing menu, click Start Compilation. The Quartus II software generates a .sof after the compilation.
Using the Reference Design: This section describes the required hardware and software setup. To run the reference design, you need the following: