System Console

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System Console

System Console

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Altera's System Console is a TCL console that provides access to hardware modules instantiated in your FPGA. You can use the System Console for all of the following purposes:

  • To create powerful verification instruments for your system
  • To start, stop, or step a Nios II processor
  • To read or write Avalon Memory-Mapped (Avalon-MM) slaves using special masters
  • To sample the SOPC system clock as well as system reset signal
  • To run JTAG loopback tests to analyze board noise problems
  • To shift arbitrary instruction register and data register values to instantiated system level debug (SLD) nodes

System Console is intended as a low level tool for tasks such as board bring up and device driver debugging. System Console along with SOPC Builder provides the framework and baseline functionality that you need to compose your own sophisticated instrumentation and verification solution.

Quick-Start Guide

System Console presents a new and unfamiliar command set; hopefully, this System Console Quick Start Guide will help ease usage for starting users.


TCL Macros

While System Console provides the low level TCL commands, a lot of useful and powerful functionality can be derived from stringing a series of commands together. Since System Console is a full fledged TCL interpreter, these can be saved as TCL Macros in file, and then the file can be sourced in the shell and used.

Please share your TCL Macros here and extend System Console's capabilties.

Preliminary Information

The following posts are pre-release information. They are not guaranteed to be accurate, nor to remain accurate, in future releases.

Beta Features

Letzte Aktualisierung:
‎06-26-2019 07:24 PM
Aktualisiert von: