System Console
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System Console
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System Console
(Redirected from SystemConsole)
Overview
Altera's System Console is a TCL console that provides access to hardware modules instantiated in your FPGA. You can use the System Console for all of the following purposes:
- To create powerful verification instruments for your system
- To start, stop, or step a Nios II processor
- To read or write Avalon Memory-Mapped (Avalon-MM) slaves using special masters
- To sample the SOPC system clock as well as system reset signal
- To run JTAG loopback tests to analyze board noise problems
- To shift arbitrary instruction register and data register values to instantiated system level debug (SLD) nodes
System Console is intended as a low level tool for tasks such as board bring up and device driver debugging. System Console along with SOPC Builder provides the framework and baseline functionality that you need to compose your own sophisticated instrumentation and verification solution.
Quick-Start Guide
System Console presents a new and unfamiliar command set; hopefully, this System Console Quick Start Guide will help ease usage for starting users.
Documentation
TCL Macros
While System Console provides the low level TCL commands, a lot of useful and powerful functionality can be derived from stringing a series of commands together. Since System Console is a full fledged TCL interpreter, these can be saved as TCL Macros in file, and then the file can be sourced in the shell and used.
Please share your TCL Macros here and extend System Console's capabilties.
- Default master - Simplified memory access commands for systems with only one memory master
- Media:New.gif Bytestream console - Given a bytestream service, displays a simple console in a separate windows.
- Fill memory - Various macros to fill a block of memory
- Hexdump - Macro to display a hexdump of memory
- bsl430.tcl - Macro to program a Texas Instrument MSP430 micro-controller, using the BootStrapLoader (BSL) feature of the MSP430. Include Quartus/SOPC project, hardware schematic, TCL macro and sample files.
- Find service by name - Macro to locate a service path by the SOPC Component name. Must use -jdi option to start system-console.
- Reset system - Macro to reset system with the first found jtag_debug service path.
- ProgrammableMaster - SOPC Builder test component which is controlled by system-console TCL scripts.
- Media:New.gif Programmable Master NEEK DDR Analysis Example - This example contains many scripts that allow you to create stimulus to the NEEK DDR memory interface with the Programmable Master component.
- Media:New.gif System Console Byte Stream Example - Using System Console to test and analyze streaming peripherals.
- Media:New.gif Avalon Fast Downloader - An example component showing how to connect from jtag to Avalon MM, with drivers for system console. Allows downloads of 200-300KBytes/sec
Preliminary Information
The following posts are pre-release information. They are not guaranteed to be accurate, nor to remain accurate, in future releases.
Beta Features
Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.
Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.
For more complete information about compiler optimizations, see our Optimization Notice.