This document describes the solution space when fitting FPGAs and how the Quartus II fitter works inside that solution space. It hopefully explains some of the reasons for variance from compile to compile. From there it describes what a seed is, and how to do seed sweeps using the Design Space Explorer.
For the most part, this document is mean to be informational. I plan on adding a follow-up document that is instructional for doing high-level optimizations using Incremental Compilation, LogicLock and advanced design analysis.