This document describes the solution space when fitting FPGAs and how the Quartus II fitter works inside that solution space. It hopefully explains some of the reasons for variance from compile to compile. From there it describes what a seed is, and how to do seed sweeps using the Design Space Explorer.
For the most part, this document is mean to be informational. I plan on adding a follow-up document that is instructional for doing high-level optimizations using Incremental Compilation, LogicLock and advanced design analysis.
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Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.