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Tips for implementing transceiver dynamic reconfiguration in 28-nm devices

Tips for implementing transceiver dynamic reconfiguration in 28-nm devices



Below is a design example details:

Device: 5AGXFB3H4F35C5 Quartus II Build: 14.0 B200

Altera IP:

1.) Transceiver Native PHY IP

2.) Transceiver Reconfiguration Controller IP

3.) Transceiver Native PHY Reset Controller IP

4.) Transceiver CMU PLL IP

5.) FPLL IP

6.) In-System Source and Probe IP

Custom Module:

1.) DBG_TOOLS.v

Script:

1.) reconfig.tcl

The attached design is last tested by using QII 14.0 B200. [Design Example]


Version history
Last update:
‎06-26-2019 12:50 AM
Updated by:
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