This design is created for evaluation purpose only. This design has passed full compilation requirement and does not target any hardware design board. This tutorial describes how to use a design flow to implement a design with multiple memory interfaces:
a) 2 DDR3 controller
b) 2 QDRII + controller
c) 2 RLDRAM controller
This design example also demonstrates how to implement Master-Slave implementation for controller in sharing resources (PLL / DLL / OCT) due to device limitation. Example for Stratix V (5SGXEABN2F45C2) device which has only 4DLLs and 4OCT calibration blocks, so resource sharing is a must.
The table below lists the specification for this design: