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Title: Multiple controller (6 controller) using UniPHY IP based controller

Title: Multiple controller (6 controller) using UniPHY IP based controller



File for this lab are located in this zip file - alterawiki.com/wiki/File:Master_Slave.qar

Design Overview:

This design is created for evaluation purpose only. This design has passed full compilation requirement and does not target any hardware design board. This tutorial describes how to use a design flow to implement a design with multiple memory interfaces:

a) 2 DDR3 controller 

b) 2 QDRII + controller 

c) 2 RLDRAM controller


This design example also demonstrates how to implement Master-Slave implementation for controller in sharing resources (PLL / DLL / OCT) due to device limitation. Example for Stratix V (5SGXEABN2F45C2) device which has only 4DLLs and 4OCT calibration blocks, so resource sharing is a must.


Design Specifications:

The table below lists the specification for this design:

AtrributeSpecification
Quartus versionQuartus II V11.1SP2
FPGA5SGXEABN2F45C2
Memory deviceDDR3: Micron MT41J128M8JP-187E
QDRII+: CY7C1243V18-375
RLDRAM: MT49H16M18-25
Memory speed gradeDDR3: 350MHz
QDRII+: 375MHz
RLDRAM: 400MHz
Memory topologyDDR3: x64 Bit
QDRII+: x18 Bit
RLDRAM: x18 Bit
IP UsedDDR3 SDRAM Controller with UniPHY IP
QDRII+ SDRAM Controller with UniPHY IP
RLDRAM SDRAM Controller with UniPHY IP



Version history
Last update:
‎06-26-2019 08:45 PM
Updated by:
Contributors