Traffic Generator 2.0: RTL workaround to support fixed pattern of Data and Byte

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Traffic Generator 2.0: RTL workaround to support fixed pattern of Data and Byte

Traffic Generator 2.0: RTL workaround to support fixed pattern of Data and Byte enables

RTL Updates to TG2.0

This document helps to explain the RTL modifications needed to support fixed patterns of Write data and byte enables in TG 2.0 through the EMIF Debug Toolkit. 

The RTL changes are necessary in two files, found under project_name/qii/ed_synth/altera_emif_tg_avl_2_160/synth directory:

  • - Required if Test data mask option is enabled in EMIF Debug Toolkit. Not required if data bytes are not masked during writes. 
  • – Required to write fixed data pattern to memory and to ensure the required data bytes are written to. 

Download files

The updated and files are available here for download:

1. RTL Updates to

This module generates the pass/fail statistics by comparing read data against expected data. The change required is to comment out the following lines shown below, in order to prevent the design from failing when the Test Datamask option has been selected. This change ensures that for a masked byte, the design does not check for a return value of 1 for bits within that byte. The design will therefore, ignore the returned data value for a masked byte. 

//else if (byteenable_stage) begin 

// pnf_per_bit[bit_num + byte_num * BYTE_SIZE] <= (rdata_rr[bit_num + byte_num * BYTE_SIZE] === 1'b1);


2. RTL Updates to

The changes involve bypassing the configured data and byte enables from the EMIF Debug Toolkit GUI and instead directly configuring them in the Verilog code based on the user parameter settings. 

This workaround is required for the following configurations:

1. Fixed pattern on Data (All pins and Individual pins case).

2. Byte enables (Default & Test data mask option enabled case - both PRBS and Fixed pattern. Necessary to ensure the desired data bytes 

1. Load parameters values:

Byte enable pattern: 

Parameter "LOAD_BE" - load the byte enable values. Default setting enables all bytes. The width of the value entered for each byte is determined by the parameter "AVL_TO_DQ_WIDTH_RATIO". A value of ‘1’ enables the byte while a value of ‘0’ disables the byte for the corresponding clock cycle. The value of 8’hFF assigned to LOAD_BE ensures data enabled in all the 8 memory clock cycles for the corresponding byte. 

// Fixed pattern to load byte enables 

parameter LOAD_BE = 8'hFF;

Fixed Data pattern:

Set parameter "FIXED_PATTERN" to either "ALL" or "INDIVIDUAL".

  • ALL – sets the same value entered for one bit to be replicated across all data pins.
  • INDIVIDUAL – allows the user to enter separate values for each data pin of the interface. 

a. "FIXED_PATTERN = ALL” - set the values to the following parameters accordingly.

  • Set the value of parameter "LOAD_PATTERN" to one of the pre-set values (ONES, ZEROS, ONES_ZEROS, ZEROS_ONES) or, set a value in parameter "LOAD_CUSTOM". 
  • The width of the value entered is determined by the parameter "AVL_TO_DQ_WIDTH_RATIO ", which is the ratio of the memory clock frequency to the user clock frequency.
  • Enter value of LOAD_CUSTOM when LOAD_PATTERN = “CUSTOM”

Following is an example of parameters set for FIXED_PATTERN = “ALL” 

parameter FIXED_PATTERN = "ALL"; 

parameter LOAD_PATTERN = "CUSTOM";

parameter LOAD_CUSTOM = 8'hC3; 

b. "FIXED_PATTERN = INDIVIDUAL" - set the value of the entire data bus on parameter "LOAD_DATA_PINS". 


For example, for an interface width of 72 data pins, and the ratio of memory clock frequency to user clock frequency is 8, MEM_DATA_WIDTH=72 and AVL_TO_DQ_WIDTH_RATIO=8. The total width of LOAD_DATA_PINS is 72*8= 576. 

Data entered in parameter LOAD_DATA_PINS for AVL_TO_DQ_WIDTH_RATIO of 8 is of the format: {[bit0,bit1,bit2 .. bit7] of data bit71,8bit word of data bit70, …8 bit word of data bit1, 8 bit word of data bit 0}br /> Following is an example of parameters to be set for FIXED_PATTERN = “INDIVIDUAL”


parameter LOAD_DATA_PINS = 576'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0;

2. Assemble data and byte enable values from parameters.

The data and byte enables are then assembled and then passed on to the data and byte enable generator logic blocks. The following code snippets show the assembling of the fixed data and byte enable patterns. 

wire [7:0] fixed_data;

wire [(DATA_PATTERN_LENGTH*NUMBER_OF_DATA_GENERATORS)-1 : 0] load_data; //576 bits

wire [BYTE_EN_PATTERN_LENGTH-1 : 0] load_be;

// in the “FIXED_PATTERN=ALL” case based on the LOAD_PATTERN chosen for the Fixed pattern, load fixed_data 


  if ( LOAD_PATTERN == "ONES") begin

    assign fixed_data = 8'hFF ;

  end else if ( LOAD_PATTERN == "ZEROS") begin

    assign fixed_data = 8'h00 ;

  end else if ( LOAD_PATTERN == "ONES_ZEROS") begin

    assign fixed_data = 8'hAA ;

  end else if ( LOAD_PATTERN == "ZEROS_ONES") begin

    assign fixed_data = 8'h55 ;

  end else if ( LOAD_PATTERN == "CUSTOM") begin

    assign fixed_data = LOAD_CUSTOM ;

  end else begin

    assign fixed_data = 8'hFF;



// load_data has the final data based on the selections made earlier. 

genvar n;


  if (FIXED_PATTERN == "ALL") begin

    assign load_data = {(NUMBER_OF_DATA_GENERATORS){fixed_data}};

  end else if (FIXED_PATTERN == "INDIVIDUAL") begin

    for (n = 0; n < NUMBER_OF_DATA_GENERATORS; n++) begin: fixed_individual_data

      assign load_data[(((n+1)*DATA_PATTERN_LENGTH) - 1) : (n*DATA_PATTERN_LENGTH)] = LOAD_DATA_PINS[(((n+1)*DATA_PATTERN_LENGTH) - 1) : (n*DATA_PATTERN_LENGTH)];


    end else begin

      assign load_data = {(MEM_DATA_WIDTH*DATA_RATE_WIDTH_RATIO){1'b1}};



//load_be has the final byte enables value

assign load_be = (byte_en_gen_mode[0])? LOAD_BE : (amm_cfg_writedata_r[BYTE_EN_PATTERN_LENGTH-1 : 0]);

3. Pass assembled data/byte enable values to the corresponding modules that generate the data and byte enables to the memory and for comparison.

The following code snippet shows the byte enables and data being loaded into the data and byte enable generators to the memory. This also needs to be done for the data written to the comparison logic as well. 


for (i = 0; i < NUMBER_OF_BYTE_EN_GENERATORS_LOCAL; i = i + 1) begin: gen_wr_byte_en_pppg

altera_emif_avl_tg_2_per_pin_pattern_gen #(



  .DEFAULT_MODE (1'b1),


) per_pin_pattern_gen_be(

  .clk (clk),

  .rst (rst),

  .load (byte_en_load[i]),

  .load_mode (1'b1),

  //Changes to bypass Toolkit values entered for data and byte enables

  //.load_data (amm_cfg_writedata_r[BYTE_EN_PATTERN_LENGTH-1:0]),

  .load_data (load_be),

  .load_inversion (1'b0),

  .enable (next_data_write),

  .dout (fixed_write_be[i]),

  .state_out ()





//data for comparison to read data

for (i = 0; i < NUMBER_OF_DATA_GENERATORS; i = i + 1) begin: exp_data_pppg

altera_emif_avl_tg_2_per_pin_pattern_gen #(



  //default to prbs pattern mode

  .DEFAULT_MODE (1'b0),

  .DEFAULT_STATE ({{(DATA_PATTERN_LENGTH-1){1'b0}}, 1'b1})



  .clk (clk),

  .rst (rst),

  .load (data_gen_load[i]),

  //takes same initial configuration as the write data generators

  .load_mode (1'b1),

  //.load_data (amm_cfg_writedata_r[DATA_PATTERN_LENGTH-1:0]),

  .load_data ((data_gen_mode[0])?(load_data[(i+1)*DATA_PATTERN_LENGTH -1:(i*DATA_PATTERN_LENGTH)]):(amm_cfg_writedata_r[DATA_PATTERN_LENGTH-1:0])),

  .load_inversion (1'b0),

  .enable (next_read_data_en),

  .dout (fixed_exp_write_data[i]),

  //only used for passing out initial configuration data through

  //this is done by the write data generators

  //unnecessary state_out

  .state_out ()




Version history
Last update:
‎06-26-2019 08:44 PM
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