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Transceiver Design Examples

Transceiver Design Examples




This page collects all of the design examples offered on the Altera wiki.


Stratix V

10GBase-KR

A template for implementing the 1G/10G Ethernet PHY IP (v13.0 SP1) in Stratix V designs.

Version history
Last update:
‎06-26-2019 01:13 AM
Updated by:
Contributors