This Level 2 article serves to guide the user through the creation, instantiation, connection, and use of the Reconfiguration Controller as a part of a complete transceiver design. This article is a part of the complete Transceiver Design Flow series of articles.
The Reconfiguration Controller is a functional block in a transceiver design that is communicates to the Tranceiver PHY IP as well as an Avalon MM Master. The controller dynamically reconfigures analog settings in Stratix V devices by writing to the Reconfiguration Control Space. Reconfiguration allows you to compensate for variations due to process, voltage, and temperature (PVT) in 28-nm devices. It is required for Stratix V devices that include transceivers. For more information including technical details (in particular how to interface the controller with the PHY IP), see Chapter 12 of the Altera Transceiver PHY IP Core User Guide or this Application Note for an step by step example of using the Controller. Also see the Dynamic Reconfiguration Guide for details on reconfiguration.
To generate the Reconfiguration Controller design files, open the MegaWizard Plugin Manager (see figure 1-1). Select "Create a new custom megawizard variation" (see figure 1-2). Under the Interfaces > Transceiver PHY will be an option for Transceiver Reconfiguration Controller (see figure 1-3). Choose a name for the output files and click "Next." The next screen (figure 1-4) will display a block diagram of the controller with it's ports shown and in this screen you will be able to customize parameters for the controller. For an explanation of each parameter, see chapter 12 of the Altera Transceiver PHY IP Core User Guide .
When finnished entering your desired parameters, hit the "Finish" button.
Figure 1-1: Quartus MainScreen
Figure 1-2: Megawizard Main Screen
Figure 1-3: Choosing a PHY IP To Generate
Figure 1-4: Customizing the Parameters for the Reconfiguration Controller
At this point, there should be 4 new items in your project directory. Quartus generates a<phy_ip_instance_name> folder, a<phy_ip_instance_name_sim> folder,<phy ip instance name>.qip, and a phy_ip_instance_name.v. The folders contain lower level design files used in compilation, and the phy_ip_instance_name.v is the top level design file.
The Interface that allows the Reconfiguration Controller to communicate with the Reconfiguration Control Space within the Transceiver PHY IP is known as the Reconfiguration Interface. The user must create the appropriate signals in the top level module, and connect the Transceiver PHY IP and the Reconfiguration Controller using these signals. It conforms to the Avalon MM Specification. See the Reconfiguration Interface sub-section of chapter 12 of the Altera Transceiver PHY IP Core User Guide for a list and description of the signals that make up the interface.
Alternatively, and if the user is choosing to perform reconfiguration using a .mif file, the user can implement the MIF Reconfiguration Management Avalon MM Master Interface. See See the MIF Reconfiguration Management Avalon MM Master Interface sub-section of chapter 12 of the Altera Transceiver PHY IP Core User Guide for a list and description of the signals that make up the interface. See the MIF sub-section of chapter 12 in the Transceiver PHY IP Core User Guide.
The Reconfiguration Management Interface is a user coded Avalon-MM slave interface that connects the Avalon MM Master to the Reconfiguration Interface. You can use an embedded controller to drive this interface. Alternatively, you can use a user coded finite state machine to control all Avalon-MM reads and writes to the Transceiver Reconfiguration Controller through this interface. This interface provides access to the Transceiver Reconfiguration Controller’s Avalon-MM registers. The interface must follow the Avalon MM Specification. See the Reconfiguration Management Interface sub section of chapter 12 of the Altera Transceiver PHY IP Core User Guide for a list and description of the signals that make up the interface.
The Transceiver Reconfiguration Controller provides two modes to dynamically reconfigure transceiver settings:
See Chapter 12 of the Altera Transceiver PHY IP Core User Guide for more information.
Compilation of the Reconfiguration Controller requires it's own library. Use the command vlib <library_name> to make a library. Navigate to the <phy_ip_instance_name_sim> folder and open the plain_files.txt that should have been generated upon completing the MegaWizard steps. The Reconfiguration Controller design files must be compiled in the order as they appear in the plain_files.txt file. To compile a design file use the command vlog <file_name>. if the design file is not in the same directory as your compilation .Tcl script, you will have to include the file path with the file name. For details on writing a compilation script for a Transceiver PHY design in ModelSim, see theTrasnceiver Design Flow Level 2 - Compilation In ModelSim article.
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