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Transceiver Design Flow Level 2 - The Reset Controller

Transceiver Design Flow Level 2 - The Reset Controller


Overview

This Level 2 article serves to guide the user through the creation, instantiation, connection, and use of the Reset Controller as a part of a complete transceiver design. This article is a part of the Transceiver Design Flow series of articles.

Required Materials

Documentation

  • Stratix V Documentation - Use this for information on Stratix V device architecture.
  • Transceiver Configurations in Stratix V Devices - Provides the transceiver channel datapath, clocking guidelines, channel placement guidelines, and a brief description of protocol features supported in each transceiver configuration for Stratix V devices.
  • Altera Transceiver PHY IP Core User Guide   - Provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera PHY IP core. The Altera IP Library is installed as part of
  • the Quartus II installation process. You can select and parameterize any Altera IP core from the library using the MegaWizard in Quartus II.
  • Avalon Specification - This document defines interfaces appropriate for streaming high-speed data, reading and writing registers and memory, and controlling off-chip devices.
  • Transceiver Reset Control in Stratix V Devices - This chapter provides the recommended transceiver initialization and reset sequencefor Stratix V devices.

What Is It?

The Reset Controller is a functional block in a transceiver design that is either external to the Tranceiver PHY IP or is internal to the Transceiver PHY IP. Depending on which PHY IP you are generating, you may have the choice of using either an internal or external controller, or you may be limited to using only an internal controller or only an external controller. To see whether the Transceiver PHY that you are implementing includes the Reset Controller, look in the protocol specific chapter of the Altera Transceiver PHY IP Core User Guide   as well as Chapter 13.


The Transceiver PHY Reset Controller IP Core is a part of the MegaWizard generated PHY IP. It is a highly configurable core that you can use to reset transceivers in Stratix V devices. It handles all reset sequencing of the transceiver to enable successful operation. For more information on the external Transceiver PHY Reset Controller, including technical details, see Chapter 13 of the Altera Transceiver PHY IP Core User Guide   and the Reset Control Guide

Generating the Reset Controller

To generate the Reset Controller design files, open the MegaWizard Plugin Manager (see figure 1-1). Select "Create a new custom megawizard variation" (see figure 1-2). Under the Interfaces > Transceiver PHY will be an option for Transceiver Reset Controller (see figure 1-3). Choose a name for the output files and click "Next." The next screen (figure 1-4) will display a block diagram of the controller with it's ports shown and in this screen you will be able to customize parameters for the controller. For an explanation of each parameter, see chapter 13 of the Altera Transceiver PHY IP Core User Guide .

When finnished entering your desired parameters, hit the "Finish" button. 


Figure 1-1: Quartus MainScreen

5/52/Quartus_main_screen.png


Figure 1-2: Megawizard Main Screen

3/3e/Megawizard_Main_Screen.png


Figure 1-3: Choosing a PHY IP To Generate

7/79/Megawizard_Protocols.png

Figure 1-4: Customizing the Parameters for the Reconfiguration Controller

 6/63/Reset_Controller_Generation.png


At this point, there should be 4 new items in your project directory. Quartus generates a<phy_ip_instance_name> folder, a<phy_ip_instance_name_sim> folder,<phy ip instance name>.qip, and a phy_ip_instance_name.v. The folders contain lower level design files used in compilation, and the phy_ip_instance_name.v is the top level design file. 


Connecting to the Transceiver PHY IP (If an external reset controller is used) 

The group of signals that allows the Reset Controller to communicate with the Transceiver PHY is described in the Interfaces sub-section of Chapter 13 of the Altera Transceiver PHY IP Core User Guide  . The user must create the appropriate signals in the top level module, and connect the Transceiver PHY IP to the Reset Controller using these signals.  

Using the Reset Controller

As long as the parameters of the Reset Controller have been set correctly, all that the user has to do is to provide a clock signal and a reset signal to the external Reset Controller in order for it to correctly reset the Transceiver PHY IP. See Chapter 13 of the Altera Transceiver PHY IP Core User Guide   for more information.

Compilation in ModelSim

Compilation of the Reset Controller requires it's own library. Use the command vlib <library_name> to make a library. Navigate to the <phy_ip_instance_name_sim> folder and open the plain_files.txt that should have been generated upon completing the MegaWizard steps. The Reset Controller design files must be compiled in the order as they appear in the plain_files.txt file. To compile a design file use the command vlog <file_name>. if the design file is not in the same directory as your compilation .Tcl script, you will have to include the file path with the file name. For details on writing a compilation script for a Transceiver PHY design in ModelSim, see theTrasnceiver Design Flow Level 2 - Compilation In ModelSim article.

Key Words

Stratix V, PCIE PIPE PHY IP, Tranceiver Reconfiguration Controller, Physical layer, PCI Express, Express, Stratix Five, GT, GS, GX, Design, Example, guide, walkthrough,

PCIe, PCI E, PCI Express, Stratix V, SV, S, V, Walkthrough, guide, help, Stratix V GX, Stratix V GT, SV, SVGX, SVGT, S5GX, S5GT, S5, Stratix 5, Stratix 5 GX, StratixV, StratixV GX, Stratix5, Stratix5 GX, Altera, generated, generation, Instantiation, creation, design, files, Reset, Control, Controller



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