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Transceiver Design Flow Level 2 - The Transceiver PHY IP

Transceiver Design Flow Level 2 - The Transceiver PHY IP

Overview

This Level 2 article serves to guide the user through the creation, instantiation, connection, and use of a Transceiver PHY IP as a part of a complete transceiver design. This article is a part of the complete Transceiver Design Flow series of articles. 

Required Materials

Documentation

  • Stratix V Documentation - Use this for information on Stratix V device architecture.
  • Transceiver Configurations in Stratix V Devices - Provides the transceiver channel datapath, clocking guidelines, channel placement guidelines, and a brief description of protocol features supported in each transceiver configuration for Stratix V devices.
  • Altera Transceiver PHY IP Core User Guide   - Provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera PHY IP core. The Altera IP Library is installed as part of
  • the Quartus II installation process. Includes technical details about each PHY IP available for use. You can select and parameterize any Altera IP core from the library using the MegaWizard in Quartus II.
  • Avalon Specification - This document defines interfaces appropriate for streaming high-speed data, reading and writing registers and memory, and controlling off-chip devices.

What Is It?

The Transceiver PHY IP is a functional block in a transceiver design that transmits and receives data, and processes it. It is the heart of the Physical Layer in a complete transceiver design. It often contains the PCS, PMA, Reset Controller, and an Avalon MM PHY Management Module, but this depends on which PHY IP you choose to instantiate. Refer to your protocol specific chapter of the Altera Transceiver PHY IP Core User Guide   for more technical details.


Generating The PHY IP

To generate the Transceiver PHY IP design files, open the MegaWizard Plugin Manager (see figure 1-1). Select "Create a new custom megawizard variation" (see figure 1-2). Under the Interfaces folder, will be many protocol specific PHY IP's(see figure 1-3). Choose a name for the output files and click "Next." The next screen (figure 1-4) will display a block diagram of the IP with it's ports shown and in this screen you will be able to customize parameters for the IP. For an explanation of each parameter, see the protocol specific chapter of the Altera Transceiver PHY IP Core User Guide 

When finnished entering your desired parameters, hit the "Finish" button. 


Figure 1-1: Quartus MainScreen

5/52/Quartus_main_screen.png


Figure 1-2: Megawizard Main Screen

3/3e/Megawizard_Main_Screen.png


Figure 1-3: Choosing a PHY IP To Generate

7/79/Megawizard_Protocols.png

Figure 1-4: Customizing the Parameters for the Transceiver PHY IP (PCIe PHY IP used in this example screenshot - your specific PHY IP Generation page will look different)

 3/3e/IP_Generation.png


At this point, there should be 4 new items in your project directory. Quartus generates a<phy_ip_instance_name> folder, a<phy_ip_instance_name_sim> folder,<phy ip instance name>.qip, and a phy_ip_instance_name.v. The folders contain lower level design files used in compilation, and the phy_ip_instance_name.v is the top level design file. 


Compilation in ModelSim

Compilation of the Transceiver PHY IP requires it's own library. Use the command vlib <library_name> to make a library. Navigate to the <phy_ip_instance_name_sim> folder and open the plain_files.txt that should have been generated upon completing the MegaWizard steps. The Transceiver PHY IP design files must be compiled in the order as they appear in the plain_files.txt file. To compile a design file use the command vlog <file_name>. if the design file is not in the same directory as your compilation .Tcl script, you will have to include the file path with the file name. For details on writing a compilation script for a Transceiver PHY design in ModelSim, see theTrasnceiver Design Flow Level 2 - Compilation In ModelSim article.

Key Words

Stratix V, PCIE PIPE PHY IP, Tranceiver Reconfiguration Controller, Physical layer, PCI Express, Express, Stratix Five, GT, GS, GX, Design, Example, guide, walkthrough,

PCIe, PCI E, PCI Express, Stratix V, SV, S, V, Walkthrough, guide, help, Stratix V GX, Stratix V GT, SV, SVGX, SVGT, S5GX, S5GT, S5, Stratix 5, Stratix 5 GX, StratixV, StratixV GX, Stratix5, Stratix5 GX, Altera, generated, generation, Instantiation, creation, design, files,


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