Dedicated on-chip transceivers can seem daunting to work with, but some simple hands-on experience can help explain how they work and how to begin designing with them. This page is intended to be the transceiver-equivalent of the common 'Hello World!' program that is used when first working with a new programming language, processor, compiler, etc.. Included is a zip-file that contains all source code, simulation compilation scripts, and a Quartus II project that together allow you to simulate the design and also generate a programming file that is ready to be loaded onto an Altera Stratix V Development Kit.
The Quartus II project also includes a SignalTap II file to inspect the functionality of the transceivers similar to the waveform result available in simulation. Taken together this design and page will introduct you to a simple transceiver implementation that you can use as a starting point to build more complex transeiver designs.
The link below can be used to download the compressed zip-file containing all files needed from both simulation and the Quartus II v12.1 project:
The files contained in the zip-file make use of relative paths so that it can be uncompressed in an root folder on your PC or Linux/UNIX system. There is a single variable in the top-level compilation script which should be tailored to the installation path for your version of Quartus II v12.1 (build 177), but this will be explained in more detail later on this page. Below is an explanation of the 4 subdirectories/folders that are created once you have uncompressed this zip-file:
|\QuartusII_v121_b177||Contains all files related to the Quartus II v12.1 (build 177) project|
|\Sim||Contains the top-level simulation compilation/invokation script as well as the testbench that instantiates the FPGA|
|\Source_HDL||All non-MegaWizard-generated files including the FPGA top-level|
|\Source_MegaCores||All MegaWizard-generated files including the transceiver instance|
The simulation platform for this example design is ModelSim-Altera v10.1b that comes with Quartus II v12.1. Other simulation platforms can be used, but will require some work to tailor the compilation scripts and environment for that platform. If you have either ModelSim-Altera or the full version of ModelSim PE/SE, you will be able to perform simulation easily and quickly without and modifications to the files contained here.
Once you have uncompressed the zip-file within this page, follow these steps to perform simulation:
This last step #4 directs ModelSim to begin executing the commands contained within the .tcl script. These will setup the simulation libraries, call Quartus-generated compilation scripts for each MegaCore (within the \Source_MegaCores directory) and also compile the non-MegaCore HDL files (within \Source_HDL), invoke the testbench, call a predefined waveform file of signals to inspect within ModelSim, 'force' a shorter reset duration for the simulation, and then run the simulation for 75 microseconds. The top-level simulation compilation script (compile_and_run_sim.tcl) is a good set of steps to inspect and modify to change how simulation is performed and also to understand what is happening at each step of the .tcl script from start to finish.
DEBUG TIP: If for any reason the simulation does not compile and complete as expected, comment-out all lines of the "compile_and_run_sim.tcl" script, and re-do step #4 above again. Because all portions of the .tcl script are commented-out, nothing should happen within ModelSim (because there are no executable commands within the .tcl script). At this point you can then begin un-commenting each line, one-by-one from top-to-bottom, and re-doing step #4 above again. This line-by-line iterative approach will allow you to easily debug what is happening that is not expected so you can change or correct that portion of the .tcl script. Below is a screenshot of the resulting waveform window:
You'll notice that different signals are grouped according to their hierarchy within the testbench and design. Some portions of the testbench to note are:
The Quartus II project will perform both synthesis and place-and-route to convert the input HDL into logic gates that can be mapped into an Altera Stratix V FPGA as well as the routes between these gates that conform to the routing that exists within the Stratix V FPGA. The current FPGA and pinout specified in the project correspond to the Stratix V GX FPGA Development Kit (part number DK-DEV-5SGXEA7N0C). The HSMC loopback daughter cards should be installed on the HSMC connectors which will loop-back the transceiver TX/RX I/O so that the FPGA will receive its own transmitted data, similar to the simulation above. The project also contains a SignalTap II file (stp1.stp) which will allow you to inspect the process of bitslip similar to the simulation. Be aware that bitslip in both simulation and on the physical FPGA will stop when it aligns to the expected pattern, but the number of shifts or 'slips' will be different. This is due to the differences between the ideal simulation and the physical world. For instance, in simulation you will see the exact same number of shifts/slips each time you run the functional simulation because it does not incorporate any timing information.However, on actual hardware there are minute timing delays within the FPGA and both the transmit and receive portions of the transceiver will assert their 'tx_ready' and 'rx_ready' at slightly different times as they come out of reset. These slight timing and reset delays will cause the actual bitslip process on hardware to take a different amount of shifts/slips each time the FPGA is programmed. It is actually very instructive to to multiple sets of programming the FPGA and observing the SignalTap II file to see that the initially-received pattern and the number of bitslipts to achieve alignment change.
If you do not have the exact Altera Stratix V Development Kit mentioned here it is possible to change the project and characteristics to conform to either a different Devlopment Kit, device family (such as Arria II or Cyclone V), or your own custom hardware. If no external loopback path exists it is also possible to setup a loopback path within the FPGA ("internal serial loopback").
Once you have successfully performed both simulation and a similar verification of the transceiver on hardware you can begin to make the design more complex. Suggestions include: