Major Release - May 3rd 2012 - version 1.0 - added SV and ATX PLL support
This article discusses a common issue of determining the phase noise jitter due to the reference clock in a typical transceiver application. Altera devices or transceivers usually specify the requirements of the reference clock in a table (see Figure 1) of offset frequency vs phase noise (dBc/Hz) however for many applications/protocols this specification is too general or too strict.
Figure 1: Example SIV REFCLK phase noise specification (from SIV Device Handbook, see latest Handbook for up to date specification)
To allow for a more accurate specification of reference clock phase noise, Altera has created a calculator tool where the user can enter their design configuration and estimate the impact the reference clock is having on the transmitter output jitter. Note that this is the primary purpose of this tool and the calculated jitter value is an ideal case approximation. Also be aware that this jitter is random jitter (RJ) only due to the phase noise from the reference clock and transmitter PLL, other factors in the system may effect this number.
To simplify the calculator and reduce the massive amount of data that would be required to accurately assess every PLL configuration, the calculator uses ideal jitter numbers to determine the worse case contribution from the reference clock. That is, when the PLL intrinsic phase noise is at its lowest, the reference clock’s phase noise will contribute a bigger percentage to the total. The calculator shows the PLL settings under which the ideal phase noise is determined. If the user is not using these settings then it can be assumed that the contribution to phase noise from the reference clock will be less than determined by the calculator as the PLL intrinsic phase noise will be higher
Please carefully note the assumptions and limitations listed below.
The calculator is Matlab driven and requires the Matlab Compiler Runtime (MCR) engine v7.17. It can be installed without a license and can be downloaded from here:
The calculator executable is here:
Total Jitter (TJ) on a transceiver output is made up of deterministic jitter (DJ) summed with random jitter (RJ). One source of RJ is from the phase noise of the reference clock and the Tx channel's PLL. See figure 2 for a simple diagram.
Figure 2: Basic PLL diagram d/dd/Phase_noise_in_PLL.jpg
The phase noise output of the PLL can be approximated as Pout = Pin + Pdiv + Pcp + Pvco +Plf where Pin is the input phase noise from the reference multiplied by the closed loop gain function (Gloop). Other components are the effects of the PLL sub blocks. We can sum these sub blocks into one number call Pintrinsic so:
Pout = Pref x Gloop + Pintrinsic
The output phase noise can be converted into phase jitter by integrating the area under the phase noise curve for each data point and taking the sum of root squares providing a psec (rms) value.
No installation is required to run the calculator itself, however the calculator requires the Matlab Compiler Runtime engine (v7.17) be installed (see above)
Double click the .exe, the calculator may take a minute or so to load as the Matlab Compiler Runtime engine will first launch in the background.
The calculator GUI looks similar to this: a/a4/Ref_Clock_Jitter_Calculator_GUI_Image.jpg
The entry fields are as follows:
The calculator will automatically update the results each time a value is changed.
The calculator will automatically save the current settings when exiting and reload these when the calculator is started next. Users can also save and load data sets to .mat files under the File menu.
The tool calculates four phase noise jitter values in the system, all measured as psec (rms):
The calculator does not determine if the jitter estimated on the Tx output is good or bad. This is up to the user depending on their system link, protocol specification or other requirements etc. It's important to note that some protocols like PCIe set specifications of random jitter for the reference clock itself, as well as the Tx out. In these protocols, to meet compliance the reference clock should meet the required spec, the calculator could be used to determine the random jitter if only the phase noise information is available for the reference clock.
The plot window shows the phase noise vs offset frequency at various points in the analysis.
For a typical xtal oscillator reference clock users will notice that it's phase noise has minimal effect on the Tx output jitter. This is expected for several reasons:
The passband between the PLL's low pass filter cutoff and the CDR's high pass filter cutoff is in the approximate range between 1 to 10MHz. Thus if the reference clock does have poor phase noise performance only this range should really matter and then only if the phase noise is around or above the level of the PLL intrinsic noise.
Currently the calculator tool only supports:
Transceivers, Reference Clock, Random Jitter, Phase Noise Jitter, CMU ATX PLL
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