Transceiver Reset Controller Timing Chart

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Transceiver Reset Controller Timing Chart

Overview

This article helps you to choose the proper parameters of the transceiver PHY reset controller by showing the simulation waveforms under different configurations.

Timing Chart

Overall - Configuration 1 to 4

c/c0/Reset_controller_tx.PNG

Configuration 1 (Channel 0): Manual Mode, 20 ns tx_digitalreset duration, Zero pll_locked hysteresis (Default settings)

4/41/Reset_controller_tx_config1_mw.png

In this configuration, the transceiver PHY reset controller reacts to only the first pll_locked assertion, even if it is a false indication. The transceiver PHY reset controller waits for the tx_digitalreset duration after the first pll_locked assertion and desserts tx_digitalreset signal. Because of the manual mode, the tx_digitalreset signal won't be asserted again even if the pll_locked signal is deasserted.

This configuration is not robust because the pll_locked signal may indicate false lock on the hardware when the PLL tries to lock to the reference clock. If false lock happens, the TX PCS is driven by unstable clock, and it may result in malfunction.

b/b7/Reset_controller_tx_config1.png

Configuration 2 (Channel 1): Auto Mode, 20 ns tx_digitalreset duration , Zero pll_locked hysteresis

5/5e/Reset_controller_tx_config2_mw.png

In this configuration, the transceiver PHY reset controller reacts to all pll_locked assertion and deassertion. The transceiver PHY reset controller waits for the tx_digitalreset duration after the pll_locked assertion and deasserts tx_digitalreset signal. Because of the auto mode, the tx_digitalreset signal is asserted if the pll_locked signal is deasserted.

7/74/Reset_controller_tx_config2.png

Configuration 3 (Channel 2): Manual Mode, 20 ns tx_digitalreset duration, 10 us pll_locked hysteresis

e/e8/Reset_controller_tx_config3_mw.png

In this configuration, the reaction is similar to the configuration 1. The difference from the configuration 1 is that the reset controller ignores shorter pll_locked high pulse than the pll_locked hysteresis value (10 us in this case). To set proper hysteresis value, refer to tpll_lock time in the device handbook/user guide.

7/76/Reset_controller_tx_config3.png

Configuration 4 (Channel 3): Auto Mode, 20 ns tx_digitalreset duration, 10 us pll_locked hysteresis

b/b9/Reset_controller_tx_config4_mw.png

In this configuration, the reaction is similar to the configuration 3. The difference from the configuration 3 is that the tx_digitalreset signal is asserted if the pll_locked signal is deasserted. The pll_locked hysteresis is not applied to the low pulse on the pll_locked signal.

This configuration is the safest to keep the TX PCS of the transceiver functioning.

Configuration 5 (Channel 4): Arria 10 Preset ""

In this configuration, all reset duration parameters are set to recommended values. You can use a preset in the Transceiver Reset Controller GUI to apply the recommended values to your Transceiver Reset Controller IP Core.

b/b9/Reset_controller_tx_config4_mw.png

Testbench for ModelSim

Required Materials for Quartus II software version 15.0

• Quartus II Software version 15.0
• Modelsim AE/SE 10.3d

Required Materials for Quartus Prime software version 16.1 Standard edition

• Quartus II Software version 16.1
• Modelsim IntelFPGA/SE 10.4d

Instructions

To run the testbench on ModelSim, follow the procedures.

1. Download File:Altera xcvr rst cnt Q150.zip or altera-xcvr-rst-cnt-q161.zip
2. Extract files from the zip file
3. Open ./simulation/top_run_msim_rtl_verilog.do file with a text editor
4. Change "/tools_archive/acds/15.0/145/linux64/quartus/" in line 19 with your Quartus II install directory. E.g. "c:/altera/15.0/quartus/"
5. Open ModelSim AE/SE
6. Change the directory to ./simulation
7. Type 'do top_run_msim_rtl_verilog.do' in the transcript window of the ModelSim

Note: To grab signals in the top level entity of Arria 10 Transceiver Reset Controller IP Core, you need to comment out (add # to) following lines of ./src/xcvr_top/sim/mentor/msim_setup.tcl file. The models in ./sim/mentor directory are needed only if your ModelSim software doesn't support multi language compilation but the visibility is not good against normal models in ./sim directory.

eval vlog -sv $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_native_a10_161/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages

eval vlog -sv $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_reset_control_161/sim/altera_xcvr_functions.sv" -L altera_common_sv_packages -work xcvr_top_altera_xcvr_reset_control_161

# eval vlog -sv $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_reset_control_161/sim/mentor/altera_xcvr_functions.sv" -L altera_common_sv_packages -work xcvr_top_altera_xcvr_reset_control_161

eval vlog -sv $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_reset_control_161/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work xcvr_top_altera_xcvr_reset_control_161

# eval vlog -sv $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_reset_control_161/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work xcvr_top_altera_xcvr_reset_control_161

eval vlog -sv $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_reset_control_161/sim/altera_xcvr_reset_control.sv" -L altera_common_sv_packages -work xcvr_top_altera_xcvr_reset_control_161

eval vlog -sv $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_reset_control_161/sim/alt_xcvr_reset_counter.sv" -L altera_common_sv_packages -work xcvr_top_altera_xcvr_reset_control_161

# eval vlog -sv $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_reset_control_161/sim/mentor/altera_xcvr_reset_control.sv" -L altera_common_sv_packages -work xcvr_top_altera_xcvr_reset_control_161

# eval vlog -sv $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../altera_xcvr_reset_control_161/sim/mentor/alt_xcvr_reset_counter.sv" -L altera_common_sv_packages -work xcvr_top_altera_xcvr_reset_control_161

External Reference

• Arria 10 Transceiver PHY User Guide - Refer to 'Using the Altera Transceiver PHY Reset Controller'

Keywords

altera_xcvr_reset_control, TX digital reset mode, tx_digitalreset duration, pll_locked input hysteresis, xcvr_reset_control