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Transceiver Toolkit

Transceiver Toolkit


This is the link to the Toolkit Designs on Altera.com Website


Transceiver Toolkit Designs (Unofficial)

Stratix V Toolkit Designs Compiled With QII 14.0

4 channels, 10.3125Gbps

4 channels, 11.3Gbps

7 channels, 10.3125Gbps

7 channels, 11.3Gbps


Arria V GZ Toolkit Design Compiled With QII 14.0

1 channel,10.3125Gbps

 

Enabling Transceiver Toolkit for EyeQ Access on PCIe Links

Use this Qsys design as a reference or directly to enable EyeQ for PCIe RX links. This system includ...

 

Toolkit Designs with a Twist

Stratix V, 4 channel design implementing four individually clocked channels using separate REFCLKs a...

Stratix V, 5 channel, 10.3125Gbps, CMU clocked, Single PHY instance, that includes RTL for implement...

Stratix V design implementing two individual transceivers. One is clocked direct from a dedicated tr...



How to use the Transceiver Toolkit to generate step and impulse response waveforms to aid channel analysis 

You can use the Altera Transceiver Toolkit designs to aid transceiver channel step and impulse response analysis by modifying the pattern generator file to transmit alternative low-frequency and high-frequency patterns


Replacing the standard high-frequency 0xAAAAAAAA test pattern with 0x80000000 generates a single bit impulse. Replacing the standard low-frequency 0xF0F0F0F0 test pattern with 0xFFFF0000 generates an ultra-low-frequency clock transmission which is similar to a step response.


You can edit any example Transceiver Toolkit design in the following way.


  • Configure The Transceiver Toolkit for your desired number of channels and datarate using the standard documented methods
  • Generate the QSYS environment
  • Go to the “Generate” tab in QSYS and un-tick the “Create HDL design files for synthesis” option. This is required to stop QSYS overwriting the next step. Close QSYS
  • Replace the “altera_avalon_data_pattern_generator.v” file in the “<Project_Name>\gx_link_test_system\synthesis\submodules” folder with this file.
  • From the Quartus II software menu, go to “Project > Add/Remove Files in Project”, and remove the <Project_Name).qsys file from the files list.
  • Add the <Project_Name>.qip file to the Files list
  • Compile the project, program the device, and run the Transceiver Toolkit as normal.
  • To run the impulse response, you should select the High-Frequency Tx test pattern. To run the step response, you should select the Low-Frequency Tx test pattern.


This Stratix V example design implements a single, 10.3125Gbps, ATX PLL clocked channel adapted to g...

 

Modular Toolkit Designs

By making use of the hierarchical features of QSYS, it is possible to simplify building large multi-...

 

The following example includes the following QSYS sub-modules fitted into a 66 channel 5SGXMB9R1H43C...

ATX_x1, ATX_x6, ATX_x12, ATX_x18, CMU_x1, CMU_x4, CMU_x5, CMU_x4_Bonded_xN

The full design has not been tested in hardware but individual modules have been tested in smaller d...You can download the example design here.

 

The following example includes the following QSYS sub-modules fitted into a 5SGTMC7K2F40C2ES Stratix...

ATX_x1, ATX_x6, ATX_x12, ATX_x18, CMU_x1, CMU_x4, CMU_x5

However, only the ATX_x1 and ATX_x6 modules are enabled in the top level QSYS file.

The design has been tested in hardware.You can download the example design here.[1]


 

Older Toolkit Designs

Stratix V, 4 channel, 10.3125Gbps, CMU clocked, xN line bonded design with Quartus II 12.0

Stratix V, 5 channel, 10.3125Gbps, CMU clocked, using multiple PHY instances with Quartus II 12.0

Stratix V, 5 channel, 10.3125Gbps, CMU clocked, using a single PHY instance with Quartus II 12.0

Stratix V, 6 channel, 10.3125Gbps, ATX clocked, using multiple PHY instances with Quartus II 12.0

Stratix V, 6 channel, 10.3125Gbps, ATX clocked, using a single PHY instance with Quartus II 12.0

Stratix V, 11 channel, 10.3125Gbps, ATX clocked, using a single PHY instance with Quartus II 12.0

Stratix V, 12 channel, 10.3125Gbps, ATX clocked, using a single PHY instance with Quartus II 12.0

Stratix V, 18 channel, 10.3125Gbps, ATX clocked, using multiple PHY instances with Quartus II 12.0

Arria V GX, 1 channel design with QII 12.0

Cyclone V GX, 1 channel design with QII 12.0

Arria II GX 1 channel design with QII 12.1sp1

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‎06-26-2019 01:29 AM
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