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Triple-Rate SDI II Simple Design

Triple-Rate SDI II Simple Design



New Release for Arria 10 ES3 - October 2016 - Quartus Prime Standard Edition v16.0.2 B222 

Last Major Update

New Release for Arria 10 ES1 - August 18th - Quartus II v15.0 B145 

New Release for Stratix V, Arria V and Cyclone V - June 22th 2015 - Quartus II v14.1 B186 Installed 


Design Overview

This simple design demonstrates the implementing of Triple Rate SDI II for StratixV GX, ArriaV GX, CycloneV GX devices and Arria 10 ES3. This design contains only one SDI duplex instance to demonstrate the internal loopback implementation. At the SDI TX side, it has an internal pattern generator connected and able to transmit SD, HD or 3G signals. This design is simple and easy to migrate to any development boards. This simple design is helpful to isolate the hardware related issues.

5/50/Top_Level_block_diagram.png

 note: Not SMA but SMB 


7/70/Hardware_setup.png

System Requirements

This design was compiled for Quartus II v14.1 for StratixV GX FPGA Development Kit or ArriaV GX Starter Kit or CycloneV GX FPGA Development Kit. And Quartus Prime Standard v16.0.2 for Arria 10 GX Development Kit.

Running the Design

1) Download the design files from the following links: 

File:Sample top CV 14 1.qar


File:Sample top SV 14 1.qar


File:Sample top AV 14 1.qar


File:Sample top a10 v16.0.2.qar


2) Compile the design in Quartus II v14.1/16.0.2 

3) Launch the Spf_sample_design.spf and download the .sof file 
















4) Ensure the cpu_resetn signal change to 1 in this .spf file. 

5) Change the user_dipsw[3:0] signals in .spf file to change the SDI transmit format. 

6) Monitor the rx_std, rx_frame and rx_trs signals and ensure those signals are asserted. 

7) For migration to other development boards (V-Series), please ensure the following pins assignment are changed correctly: 

a.clk_148_p


b.clk_reconfig_p


c.sdi_tx_p


d.sdi_rx_p


e.sdi_rx_bypass


f.sdi_tx_sd_hdn


g.sdi_tx_en


h.sdi_rx_en



Stratix V SDI II HD mode Simple Design simulation example

Overview

This basic design example with Modelsim simulation demonstrates the functional simulation of Stratix V SDI II simple design in HD mode. The purpose of this design example is to assist users to have quick start with the Stratix V SDI II functional simulation. Note that this simulation example has the fast mode simulation enabled which only work for simulation. You can refer to the changes done to the IS_RTL_SIM parameter in sample_top_cp.v and sdi_ii_0001.v if you compare with the actual hardware design example above.

To run the simulation, do the following:

1. Unzip the files 

2. Change the Modelsim directory to the unzipped folder 

3. Type "source simulation_setup.tcl" 

4. Type "ld" to compile 

5. Type "simulate" to start simulation 

Design File

Stratix V SDI II HD mode Simple Design simulation example Q15.1 (ZIP)     




© [2013] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.

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