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Triple Speed Ethernet SGMII Auto-negotiation Testbench

Triple Speed Ethernet SGMII Auto-negotiation Testbench


Design Overview

This testbench demonstrates Serial Gigabit Medium Independent Interface (SGMII) Auto-negotiation of Triple Speed Ethernet (TSE) IP. New feature SGMII PHY mode implemented in ACDS version 13.0 enables us to see SGMII Auto-Negotiation is completed by using only TSE IP.


Two TSE IP are instanced to establish SGMII link. One TSE IP (instance name TSE0) acts as SGMII MAC device, and another TSE IP (instance name TSE1) acts as SGMII PHY device. You can set the SGMII mode through the PCS If_Mode Register (Word Offset 0x14) bit 5 SGMII_AN_MODE


SGMII_AN_MODE

SGMII auto-negotiation mode:

1: enable SGMII PHY mode

0: enable SGMII MAC mode

This bit resets to 0, which defaults to SGMII MAC mode.

0/05/SGMII_ANEG_Block.PNG

Design File

For Quartus II version 13.1:

  1. Core Variation = 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII PCS TSE13 0 MAC PCS SGMII sim Q131.zip
  2. Core Variation = 1000BASE-X/SGMII PCS only TSE 131 PCS only 13.1.zip


For Quartus Prime version 16.0:

  1. Core Variation = 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII PCS TSE16 0 MAC PCS SGMII sim.zip

Running Simulation

To run the testbench with ModelSim, follow instructions.

  1. Extract the archive file
  2. Open ./simulation/run_altera_tse_tb.tcl with a text editor
  3. Enter proper Quartus II install directory to line 14, QUARTUS_INSTALL_DIR variable
  4. Run ModelSim
  5. Change directory to ./simulation folder.
  6. Type 'do run_altera_tse_tb.tcl' in the console of the ModelSim

f/ff/Wave.PNG

Tasks in the testbench

This is only available in the Core Variation = 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII PCS simulation testbench.

  • Configure TSE0 (SGMII MAC Mode)

tb_top.sv(70): virtual task run_config_sgmiimac();

  • Configure TSE1 (SGMII PHY Mode)

tb_top.sv(98): virtual task run_config_sgmiiphy();

  • Register Write

tb_top.sv(128): virtual task write

E.g.: write('h02, 'h008001d0); // Write 0x0080_01d0 to register word address 0x02

  • Register Read

tb_top.sv(144): virtual task read

E.g.: read ('h02 ); // Read register word address 0x02

  • Avalon-ST TX

tb_top.sv(204): virtual task send

E.g.: send (64) // Transmit 64 bytes to Avalon-ST Tx

See Also

Triple-Speed Ethernet MegaCore Function

Triple-Speed Ethernet IP Core Resource Center

Triple-Speed Ethernet MegaCore Function User Guide (PDF)

Serial-GMII Specification Revision 1.8 (ENG-46158) (PDF)

Knowledge Base: Do the LED_AN or LED_LINK signals of Triple Speed Ethernet IP Core reflect the coppe...

Key Words

Triple Speed Ethernet, TSE, SGMII, Auto-Negotiation, Auto Negotiation, SGMII_AN_MODE, MAC mode, PHY mode

Version history
Revision #:
1 of 1
Last update:
‎06-26-2019 09:23 PM
Updated by:
 
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