Triple Speed Ethernet (TSE) Cyclone V RGMII
Description
This wiki page is dedicated towards users that are using Intel PSG Cyclone V TSE (Triple Speed Ethernet) IP with RGMII interface and external PHY. There are other examples available on the web, but some do not show as timing closed. Timing closure on the RGMII source synchronous IO can be challenging and is not always done accurately leading to timing violations, passing timing with a non-functional interface, or user created false paths that incorrectly remove timing analysis that may operate in the lab at room temperature, but fail later in production across a few boards.
Example
The Cyclone V TSE RGMII design example was migrated from an Arria II GX RGMII design example found here:
https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intellectual-property/exm-tse-rgmii-phy.html
The design example was created using Quartus Standard version 17.1.1
CV TSE RGMII With SDC.qar - See attached at the bottom of this article
The timing of the interface is dependent on board layout as well as the specifications of the external PHY. The following lines should be customized in the RGMII.sdc file.
**************************************************************
# Board and External PHY
#**************************************************************
# Board Delay
# Assume trace delay, pin capacitance, and rise/fall time differences between
# data and clock are negligible.
set data_delay_max 0
set data_delay_min 0
set clk_delay_max 0
set clk_delay_min 0
# External PHY Parameter (Refer to MarvelPHY 88EE1111)
set tsu 1.0
set th 0.8
set tco_max 0.5
set tco_min -0.5
The following qsf assignment is very important to help force the output PLL clock to the TSE and external PHY onto a regional clock buffer.
set_location_assignment CLKCTRL_R27 -to "PLL_CV:pll_inst|PLL_CV_0002:pll_cv_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0]~CLKENA0"
Otherwise, a global (CLKCTGRL_G*) buffer could be chosen which will have wider skew characteristics making timing closure on the source synchronous interface through the DDIO mux select more challenging.
Keep in mind that the example on this wiki page has no pinouts assigned. So, the above assignment to a regional buffer may need to be changed based on the exact part number and location of the RGMII interface pins on the Cyclone V FPGA.
Even with the above assignment to use a regional clock buffer, Quartus may not be able to delay the RGMII TX clock output to the external PHY enough to meet timing. In those cases, the following, post fitter script is required.
D5_Delay_on_RGMII_TX_CLK.tcl
package require ::quartus::chip_planner
package require ::quartus::project
load_chip_planner_utility_commands
project_open TSE_RGMII_With_SDC -revision TSE_RGMII_With_SDC
read_netlist
set had_failure 0
############
# Index: 1 #
############
set node_id [ get_node_by_name -name |Top|RGMII_TX_CLK ]
if { $node_id == -1 } {
puts "FAIL: get_node_by_name -name |Top|RGMII_TX_CLK"
set had_failure 1
} else {
set result [ set_node_info -node $node_id -info "D5 Delay Chain" "7" ]
if { $result == 0 } {
puts "FAIL (|Top|RGMII_TX_CLK): set_node_info -node $node_id -info \"D5 Delay Chain\" \"7\""
set had_failure 1
} else {
puts "SET (|Top|RGMII_TX_CLK): set_node_info -node $node_id -info \"D5 Delay Chain\" \"7\""
}
}
puts ""
set drc_result [check_netlist_and_save]
if { $drc_result == 1 } {
puts "check_netlist_and_save: SUCCESS"
} else {
puts "check_netlist_and_save: FAIL"
}
if { $had_failure == 1 } {
puts "Not all set operations were successful"
}
project_close
The above script is in the project directory after un-archiving the example. To run the script after running the fitter:
quartus_cdb -t D5_Delay_on_RGMII_TX_CLK.tcl
If the D5 delay assignment is placed into the qsf file on a fresh compile (new db), the design may not meet timing. It will be better to run the tcl script via quartus_cdb to set the D5 delay AFTER the initial fitter.
Note: This design was not verified to run on hardware. It should be used as an example for timing constraints and how to meet timing on a Cyclone V FPGA with TSE IP and RGMII interface.
