This wiki page is dedicated towards users that are using Intel PSG Cyclone V TSE (Triple Speed Ethernet) IP with RGMII interface and external PHY. There are other examples available on the web, but some do not show as timing closed. Timing closure on the RGMII source synchronous IO can be challenging and is not always done accurately leading to timing violations, passing timing with a non-functional interface, or user created false paths that incorrectly remove timing analysis that may operate in the lab at room temperature, but fail later in production across a few boards.
The Cyclone V TSE RGMII design example was migrated from an Arria II GX RGMII design example found here:
Otherwise, a global (CLKCTGRL_G*) buffer could be chosen which will have wider skew characteristics making timing closure on the source synchronous interface through the DDIO mux select more challenging.
Keep in mind that the example on this wiki page has no pinouts assigned. So, the above assignment to a regional buffer may need to be changed based on the exact part number and location of the RGMII interface pins on the Cyclone V FPGA.
Even with the above assignment to use a regional clock buffer, Quartus may not be able to delay the RGMII TX clock output to the external PHY enough to meet timing. In those cases, the following, post fitter script is required.
The above script is in the projcet directory after un-archiving the example. To run the script after running the fitter:
quartus_cdb -t D5_Delay_on_RGMII_TX_CLK.tcl
If the D5 delay assignment is placed into the qsf file on a fresh compile (new db), the design may not meet timing. It will be better to run the tcl script via quartus_cdb to set the D5 delay AFTER the initial fitter.
Note: This design was not verified to run on hardware. It should be used as an example for timing constraints and how to meet timing on a Cyclone V FPGA with TSE IP and RGMII interface.