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Triple-rate SDI II Reference Design for Stratix V, Arria V & Cyclone V devices

Triple-rate SDI II Reference Design for Stratix V, Arria V & Cyclone V devices



Last Major Update

New Release for Stratix V , Cyclone V and Arria V - December 3rd 2015 - Quartus II Prime v15.1 B185 Installed 

New Release for Stratix V and Arria V - March 3rd 2015 - Quartus II v14.1 B186 Installed 

New Release for Cyclone V - March 13rd 2015 - Quartus II v14.1 B186 Installed 


Design Overview

This reference design demonstrates the implemention of triple rate SDI II for Stratix V GX, Arria V GX or Cyclone V GT. The Stratix V GX or Cyclone V GT design contains one SDI transmitter instance, one SDI duplex instance and one SDI receiver instance. The Arria V GX design contains one SDI transmitter instance and one SDI duplex instance only. The SDI transmitter only instances have the internal pattern generator connected and able to transmit SD, HD or 3G signals. The SDI duplex instances demonstrate the internal loopback implementation.

  • Quartus II Prime version 15.1 must be used for SDI II in Stratix V GX or Arria V GX or Cyclone V GT devices


System Requirements

This design was compiled for Quartus II Prime v15.1 for Stratix V GX FPGA Development Kit or Arria V GX Starter Kit or Cyclone V GT FPGA Development Kit with SDI HSMC daughter card.


Running the Design

1. Set up the hardware by connecting SDI HSMC daughter card into HSMC port A of Stratix V GX FPGA Development Kit or Arria V GX Starter Kit and HSMC port B of Cyclone V GT FPGA Development Kit.

  • For SDI HSMC daughter card, it is recommended to install jumpers J4(CD_MUTE2) and J6 (CD_MUTE1). This is to ensure the receiver channel 0 and channel 1 function properly. Refer to DIPSW LED PB.docx for more details on this.
  • Stratix V - Clock output from SDI HSMC daughter card (J17 & J18) need to be connected to clock input from Stratix V GX development kit (J13 & J14) with SMA cables.
  • Cyclone V - Clock output from SDI HSMC daughter card (J17 & J18) need to be connected to clock input from Cyclove V GT development kit (J3 & J6) with SMA cables.
  • Arria V - Clock output from SDI HSMC daughter card (J17 & J18) need to be connected to clock input from Arria V GX starter kit (J7 & J8) with SMA cables.

2. Ensure the board setting DIP switch on the development kit (DIP Switch [0])-CLK_SEL pin is set to 'ON' position, this indicates that SMA input clock is chosen. Refer to DIPSW LED PB.docx for more details on this.

3. Download the design file in the link below.

4. Compile the design in Quartus v15.1 for Stratix V GX FPGA Development Kit or Arria V GX Starter Kit or Cyclone V GT FPGA Development Kit

5. Configure the sof file generated into the Stratix V GX FPGA Development Kit, Arria V GX Starter Kit or Cyclone V GT FPGA Development Kit. 


HSMC SDI card instances:

  • Transmitter only instance (J8) : internal pattern generator
  • Duplex instance (J1 and J2): demonstrate internal loopback

Please refer to note below for The Switch and condition of LEDs:

DIPSW LED PB.docx

Link to the Design Files

S5gxsdi ii top.zip 

A5gxsdi ii top.zip 

C5gtsdi ii top.zip 


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Version history
Revision #:
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Last update:
‎06-26-2019 01:33 AM
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