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Triple-rate SDI Reference Design for Cyclone V devices

Triple-rate SDI Reference Design for Cyclone V devices



Last Major Update

2nd Release - July 17th 2014 - Qyartus II v13.1 B162

Initial Release - Mar 8th 2013 - Quartus II v12.1sp1.dp1 B243 Service Pack 1.dp1 Installed


Design Overview

This reference design demonstrates the implementing of triple rate SDI for Cyclone® V GX. This design contains two SDI transmitter instances, one SDI duplex instance and one SDI receiver instance. Two SDI transmitter only instances have the internal pattern generator connected and able to transmit SD , HD or 3G signals. The SDI duplex instance demostrate the internal loopback implementation by using controlling VCXO on SDI HSMC daugther card.

  • Quartus 13.1 version or later must be used for SDI in Cyclone V device


System Requirements

This design was compiled for Quartus II v12.1sp1.dp1 for Cyclone V GX FPGA Development Kit with SDI HSMC daugther card.


Running the Design

1. Set up the hardware by connecting SDI HSMC daughter card into HSMC port of Cyclone V GX development board.

2. Download the design file in the link below.

3. Compile the design in Quartus v13.1 and configure the sof file into the Cyclone V GX development board.

4. Program the sof file generated into the Cyclone V GX development board. 

On board SDI instances:

  • Transmitter only instance (J5) : internal pattern generator
  • Receiver only instance (J10)


HSMC SDI card instances:

  • Transmitter only instance (J8) : internal pattern generator
  • Duplex instance (J1 and J2): demostrate internal loopback by using controlling VCXO on SDI HSMC daugther card


The Switch and LEDs indicated the following conditions:

  • Switch DIP switch [SW2.1, SW2.2] : 11=SD ; 10=HD ; 00=3G to change internal pattern generator signal standard.
  • Switch SW2.3: 0= 75% color bar ; 1= Pathological signal 
  • Switch SW2.4: 

0= {on board receiver, J10 standard (D4, D5), On board receiver frame locked (D6), on board receiver clock out (D7) }

1= {HSMC SDI card receiver, J2 standard (D4, D5), HSMC SDI card receiver frame locked (D6), on board transmitter clock out (D7) }


  • LEDs D4, D5 indicate the receiver signal standard
  • LEDs D6 indicate the receiver frame locked.
  • LEDs D7 indicate the transmitter or receiver clock out.


  • switch ON = 0, OFF = 1.



Link to the Design Files

Download  C5gxsdi.qar

© [2013] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.

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Last update:
‎06-26-2019 01:34 AM
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