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Use Transceiver Toolkit to Measure PCI-Express Link Signal Integrity

Use Transceiver Toolkit to Measure PCI-Express Link Signal Integrity


This article explains how to integrate Altera Transceiver Toolkit (TTK) into a PCI-Express design, it allows the user to measure the receiver eye and change the receiver's CTLE setting of each active lane. All the changes and measurements can be done when the link is in L0 state and there is real PCIe traffic on the link. The TTK is a powerful tool to qualify how the signal integrity of the link is. The user can also adjust the CTLE manually and find out the best setting for each lane.

Hardware Requirements

  1. A computer which has Quartus version 13.1 or later. It will be used to open the TTK and control the FPGA through Altera USB Blaster.
  2. An Altera USB Blaster.
  3. A system which has the Altera FPGA with PCIe HIP and the HIP is able to link up to the required speed.

Software Requirements

  1. Quartus version 13.1 or later


Add TTK into the Design

1. Open the original Qsys file in Quartus, add a "JTAG to Avalon Master Bridge" into the Qsys.

2. Connect signals of the new added "JTAG to Avalon Master Bridge" to "alt_xcvr_reconfig" as shown below.


Connection of new JTAG to AVMM Master

3. Edit "alt_xcvr_reconfig", enable the options as shown below. If the design is Gen1 or Gen2, the "Enable adaptive equalization (AEQ) block" can be unselected.


Needed Options in Reconfig Controller

4. Save the Qsys file, generate the IP, copy the new generated RTL files into the folder where the Quartus will compile and synthesis, compile the design, and program the SOF into the FPGA.

Steps to run TTK

  1. Open the project in Quartus, must be 13.1 or later, installed in the computer which is connected to the FPGA through the USB blaster.
  2. Under pull down menu, select "Tools/System Console/Transceiver Toolkit", it opens the TTK window.
  3. Select "Transceiver Toolkit" tab.
  4. Select "Receiver Channels" tab, it allows you to measure and control the RX.
  5. Select the "reconfig" file in reconfig path pull down menu. If you don't see any file, it means the TTK can't detect the reconfig_controller in the design. Re-check the connection between the JTAG-to-AVMM Master and the reconfig_controller in Qsys.
  6. Add the channel number you want to measure or control into the field at the end of the Reconfig path.
  7. Click "Create Receiver Channel" icon to create the requested channel.
  8. Click "Control Receiver Channel", it opens "Receiver: Rx_channel_x" window.
  9. If the link speed is in Gen3 and the link is trained through standard PCIe link training, include EQ phase, the "Equalization Mode" should be in "one-time adaptation" as shown below. The value in "Equalization Control" field reflects the current RX CTLE setting. If the FPGA is Gen1 or Gen2 capable, since the AEQ is not enabled, so it does not show the "Equalization Mode" and the "Equalization Control" value is 0. 9/92/Capture3.PNG
  10. One-time adaptation mode is enabled for channel 0
  11. You can change the CTLE value by changing the "Equalization Mode" to "Manual". After that, you can put in any value into the "Equalization Control".
  12. For Eye measure, select "Advanced" tab.
  13. Select "EyeQ" in Test Mode.
  14. Click "Start" icon to draw the eye diagram for the lane. Below is an example of a Gen3 eye.
  15. Eye Diagram Drawn by TTK in Gen3 speed


Limitation in Quartus 13.1 and Workaround

For Quartus version 13.1, the default reconfig_driver for AEQ is not compatible with the TTK. When the TTK is added through the above steps, the reconfig_driver won't implement AEQ properly and the Equalization mode won't be in one-time adaptation mode. You must replace the in the design by the following file.

Altpcie reconfig

Such limitation is fixed in later release.

Reference Designs

This section provides some reference designs with Transceiver Toolkit, which target Altera Stratix V GX DevKit. The user can download it, compile it, and use it directly. The TTK and the required reconfig_driver file have been included.

For these reference designs, the synthesis folder is "pcie_lib". Hence, if the IP are re-generated by Qsys, copy all files (include the top.v) into "pcie_lib" directory.

Reference Design for Gen3 x8

This is a Stratix V Gen3 x8 Quartus 13.1 reference design with Transceiver Toolkit.

Target: Stratix V GX DevKit

Quartus: 13.1 

Devkit g3 x8 ast256 ttk 13.1.qar

Reference Design for Gen2 x8

This is a Stratix V Gen2 x8 Quartus 13.1 reference design with Transceiver Toolkit.

Target: Stratix V GX DevKit

Quartus: 13.1

DevKit g2 x8 ast256 ttk 13.1.qar

Reference Design for Gen1 x8

This is a Stratix V Gen1 x8 Quartus 13.1 reference design with Transceiver Toolkit.

Target: Stratix V GX DevKit

Quartus: 13.1

Devkit g1 x8 ast128 ttk 13.1.qar

Version history
Last update:
‎06-26-2019 02:24 AM
Updated by: