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User Configurable Transceiver Demo Designs

User Configurable Transceiver Demo Designs

 

Introduction

These demo designs are provided to let you quickly generate bespoke Intel FPGA transceiver systems that meet your requirements.

You can use these designs for proof of concept, transceiver schematic review IO ring designs, board bringup, debug, signal integrity tuning, and more. 

Intel Stratix 10

Intel Stratix 10 TX, E-Tile, User Configurable Transceiver Demo Design

Features

-User-configurable for any number of E-Tile transceiver PMA direct channels

-User-configurable for eight groups of NRZ and eight groups of PAM4 modulated PHYs

-Includes 9.8G, 10.1G, 10.3G, 24.3G, 25.8G, 28.3G predefined NRZ PHYs. Also includes two user NRZ PHYs

-Includes 51.5G PAM4 predefined PHYs. Also includes two user PAM4 PHYs

-Includes the ability to transmit single bit, step, and clock patterns useful for signal integrity analysis of NRZ PHYs

-Can be used with the Quartus Prime Pro Transceiver Toolkit GUI

-The Stratix 10 TX Helper Script will work with this design Ttk helper s10tx.tcl

Intel Stratix 10 GX, L-Tile and H-Tile, User Configurable Transceiver Demo Design

Features

-User-configurable for any number of GX channels (Eight duplex, four Tx simplex, and four Rx simplex groups of any number of channels)

-User-configurable for any Tx PLL type (ATX, fPLL, CMU)

-User-configurable for any unbonded serial clock

-Includes 9.8G, 10.1G, 10.3G, 11.3G, 12.5G, and 17.4G preset GX channels. Also includes four user GX channel PHYs

-Includes 24.3G, 25.8G, 28.0G, and 28.3G preset GXT channels. Also includes four user GXT channel PHYs

-Supports GXT Main and Adjacent ATX PLL clocking

-Includes the ability to transmit single bit, step, and clock patterns useful for signal integrity analysis

-Can be used with the Quartus Prime Pro Transceiver Toolkit GUI

-Will work with L-Tile ES2 and later, and H-Tile devices

-The Stratix 10 Helper Script will work with this design Ttk helper s10.tcl

Intel Arria10

Intel Arria 10 GX/SX User Configurable Transceiver Demo Design

Features

-User-configurable for any number of GX channels (Eight duplex, four Tx simplex, and four Rx simplex groups of any number of channels)

-User-configurable for any Tx PLL type (ATX, fPLL, CMU)

-User-configurable for any unbonded serial clock

-Includes 5.4G, 5.94G, 6.25G, 8.1G, 9.8G, 10.3G, 11.3G, 11.88G, and 12.5G preset GX channels. Also includes four user GX channel PHYs

-Includes the ability to transmit single bit, step, and clock patterns useful for signal integrity analysis

-Can be used with the Quartus Prime Transceiver Toolkit GUI

-The Arria 10 Helper Script will work with this design Ttk helper.tcl

Intel Cyclone 10 GX

Intel Cyclone 10 GX User Configurable Transceiver Demo Design

Features

-User-configurable for any number of GX channels (Eight duplex, four Tx simplex, and four Rx simplex groups of any number of channels)

-User-configurable for any Tx PLL type (ATX, fPLL, CMU)

-User-configurable for any unbonded serial clock

-Includes 5.4G, 5.94G, 6.25G, 8.1G, 9.8G, 10.3G, 11.3G, 11.88G, and 12.5G preset GX channels. Also includes four user GX channel PHYs

-Includes the ability to transmit single bit, step, and clock patterns useful for signal integrity analysis

-Can be used with the Quartus Prime Pro Transceiver Toolkit GUI

-The Arria 10 Helper Script should work with this design Ttk helper.tcl

Version history
Revision #:
5 of 5
Last update:
‎07-16-2020 08:58 AM
Updated by: