Using the USB-Blaster as an SOPC/Qsys Avalon-MM master Tutorial
JTAG-to-Avalon-MM Tutorial System Diagram
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This tutorial walks the user through the creation, simulation, and hardware testing of an Avalon system created using both SOPC Builder and Qsys.
Tutorial Features
- Altera JTAG-to-Avalon-MM Master
- Altera Verification IP Avalon-MM BFM Master
- Simulation using Modelsim-ASE
- Tcl synthesis scripts to automate the re-generation of the SOPC and Qsys systems
- Tcl simulation scripts to automate running the testbenches
- Hardware communication from the host PC using System Console and quartus_stp
- Example of a TCP/IP server under System Console and quartus_stp
- Example of a TCP/IP client written as a Tcl/Tk GUI and as a C command-line interface
- Synthesis examples for the BeMicro-SDK, BeMicro, and DE2
Tutorial Downloads
Feedback/Suggestions
If you liked this tutorial, or have feedback or suggestions on how it can be improved, please post a message to the Altera Forum: http://www.alteraforum.com/forum/showthread.php?t=34787
