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Vip control decoder

The vip_control_decoder is a custom component for Altera's VIP Suite that assembles the Avalon ST Video control packet data and outputs the embedded width, height, and interlacing information along with an output valid signal via conduits for use in simulation, SignalTap II, or other debugging. The component only snoops on the stream, all packet types pass through unchanged. The core may also serve as a template for building other VIP Suite components.


The core includes clear text VHDL and a hw.tcl file. When using a Verilog SOPC Builder system, a .vo simulation model is generated for use in single language simulators.


The core is configurable in SOPC Builder via the component's GUI. The bits per symbol (BITS_PER_SYM) and symbols per beat (SYM_PER_BEAT) should be set based on the video stream's specifications (number of color planes, serial/parallel, etc). These parameters are checked in real time based on the VIP Suite legal values. The MAX_WIDTH and MAX_HEIGHT parameters are not used by the vip_control_decoder block, but were included for use in derivative cores.


To use the core, unzip the file into the project's ip directory and refresh the SOPC Builder system. The vip_control_decoder component should show up at the top of the components list. Add the component to your system and connect the block in series with the video stream you would like to analyze. In the example screen shot, the vip_control_decoder is connected between the Test Pattern Generator and the Clocked Video Output to detect the frame size of the Test Pattern Generator.


The control data is output through conduits named:

  • VID_WIDTH (16 bit)
  • VID_HEIGHT (16 bit)
  • VID_INTERLACE (4 bit)
  • VID_SPECS_VALID (1 bit)


For accurate resource usage and performance numbers, please compile a test design with vip_control_decoder set as the top level entity with your target device selected. Estimated resource usage is around 125 LEs. Cyclone II slowest speed grade (8) performance is estimated just under 200 MHz and Stratix III slowest speed grade (4) is just under 400 MHz.


vip_control_decoder was written for Quartus II 9.1, but should be forwards compatible. The archive contains Mercurial distributed revision control.


Updated 20101026. Verified on hardware. Check Mercurial version history/diff.

File:Vip control decoder.zip


Please report any bugs on the discussion page of this entry, my talk page, on the Altera Forum, or in a private message to thepancake on the Altera Forum.


To do list for the vip_control_decoder:

  1. Use the VIP Suite Avalon Streaming terminology (series/parallel, number of planes) instead of beats per symbol
  2. Add more documentation
  3. Create new "VIP VHDL Template" wiki entry so the below can be removed from this core
  4. Remove the MAX_WIDTH and MAX_HEIGHT since they are unused
  5. Remove the chk_pkt, data_pkt, and other_pkt signals which cause compilation warnings since they are unused
  6. Remove EOP if statement since it is unused


Version history
Revision #:
1 of 1
Last update:
‎10-22-2019 08:57 PM
Updated by:
 
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