Stratix II and beyond do not have a ZBT OE control circuit in the IO for use with ZBT SRAMs, only Stratix I had this. I did some analysis awhile back for a one bus turnaround solution with ZBT SRAM. The results can be used for SII, SIIGX, etc. A write up and verilog ZBT SRAM controller design and testbench are attached. ZBT SRAM bus functional models were used for timing simulation but they are removed from the zip file for licensing reasons.
This solution uses a single cycle turnaround between reads and writes, so its not really ZBT but for the system I was using, I was reading 95% of the time so this cycle latency turnaround didn't affect my efficiency much. IP is here free for others to use.
Another option is to create your own ZBT delay for the OE signal - perhaps with a 2x clock controlling the OE so the turn on time is delayed a bit. Didn't investigate this further, but an idea that could be built upon if someone really wants to build custom ZBT interface in newer families.